| From e0fbe1b3abb3808ae259d49cbfcf8ab680f5a8d2 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 14 Apr 2021 14:45:43 +0200 |
| Subject: openrisc: Define memory barrier mb |
| |
| From: Peter Zijlstra <peterz@infradead.org> |
| |
| [ Upstream commit 8b549c18ae81dbc36fb11e4aa08b8378c599ca95 ] |
| |
| This came up in the discussion of the requirements of qspinlock on an |
| architecture. OpenRISC uses qspinlock, but it was noticed that the |
| memmory barrier was not defined. |
| |
| Peter defined it in the mail thread writing: |
| |
| As near as I can tell this should do. The arch spec only lists |
| this one instruction and the text makes it sound like a completion |
| barrier. |
| |
| This is correct so applying this patch. |
| |
| Signed-off-by: Peter Zijlstra <peterz@infradead.org> |
| [shorne@gmail.com:Turned the mail into a patch] |
| Signed-off-by: Stafford Horne <shorne@gmail.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/openrisc/include/asm/barrier.h | 9 +++++++++ |
| 1 file changed, 9 insertions(+) |
| create mode 100644 arch/openrisc/include/asm/barrier.h |
| |
| diff --git a/arch/openrisc/include/asm/barrier.h b/arch/openrisc/include/asm/barrier.h |
| new file mode 100644 |
| index 000000000000..7538294721be |
| --- /dev/null |
| +++ b/arch/openrisc/include/asm/barrier.h |
| @@ -0,0 +1,9 @@ |
| +/* SPDX-License-Identifier: GPL-2.0 */ |
| +#ifndef __ASM_BARRIER_H |
| +#define __ASM_BARRIER_H |
| + |
| +#define mb() asm volatile ("l.msync" ::: "memory") |
| + |
| +#include <asm-generic/barrier.h> |
| + |
| +#endif /* __ASM_BARRIER_H */ |
| -- |
| 2.30.2 |
| |
