| From 78c90cb75dd51555a108ddd9b347df3ac9d521db Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 3 Jul 2025 10:51:19 -0700 |
| Subject: drm/msm: Update register xml |
| |
| From: Rob Clark <robin.clark@oss.qualcomm.com> |
| |
| [ Upstream commit 6733d8276ac02a8790e571d2af4a69a9039d0522 ] |
| |
| Sync register xml from mesa commit eb3e0b7164a3 ("freedreno/a6xx: Split |
| descriptors out into their own file"). |
| |
| Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> |
| Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> |
| Patchwork: https://patchwork.freedesktop.org/patch/662470/ |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/msm/Makefile | 5 + |
| drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2 +- |
| drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 + |
| drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- |
| drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +- |
| drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 2 +- |
| .../drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 4 +- |
| drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 3582 +++-------------- |
| .../msm/registers/adreno/a6xx_descriptors.xml | 198 + |
| .../drm/msm/registers/adreno/a6xx_enums.xml | 383 ++ |
| .../msm/registers/adreno/a6xx_perfcntrs.xml | 600 +++ |
| .../drm/msm/registers/adreno/a7xx_enums.xml | 223 + |
| .../msm/registers/adreno/a7xx_perfcntrs.xml | 1030 +++++ |
| .../drm/msm/registers/adreno/adreno_pm4.xml | 302 +- |
| 14 files changed, 3312 insertions(+), 3027 deletions(-) |
| create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml |
| create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml |
| create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.xml |
| create mode 100644 drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml |
| create mode 100644 drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.xml |
| |
| diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile |
| index 7a2ada6e2d74..44c66a293415 100644 |
| --- a/drivers/gpu/drm/msm/Makefile |
| +++ b/drivers/gpu/drm/msm/Makefile |
| @@ -195,6 +195,11 @@ ADRENO_HEADERS = \ |
| generated/a4xx.xml.h \ |
| generated/a5xx.xml.h \ |
| generated/a6xx.xml.h \ |
| + generated/a6xx_descriptors.xml.h \ |
| + generated/a6xx_enums.xml.h \ |
| + generated/a6xx_perfcntrs.xml.h \ |
| + generated/a7xx_enums.xml.h \ |
| + generated/a7xx_perfcntrs.xml.h \ |
| generated/a6xx_gmu.xml.h \ |
| generated/adreno_common.xml.h \ |
| generated/adreno_pm4.xml.h \ |
| diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c |
| index 70f7ad806c34..a45819e04aab 100644 |
| --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c |
| +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c |
| @@ -1335,7 +1335,7 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { |
| REG_A6XX_RB_NC_MODE_CNTL, |
| REG_A6XX_RB_CMP_DBG_ECO_CNTL, |
| REG_A7XX_GRAS_NC_MODE_CNTL, |
| - REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, |
| + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, |
| REG_A6XX_UCHE_GBIF_GX_CONFIG, |
| REG_A6XX_UCHE_CLIENT_PF, |
| REG_A6XX_TPL1_DBG_ECO_CNTL1, |
| diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h |
| index 9201a53dd341..6e71f617fc3d 100644 |
| --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h |
| +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h |
| @@ -6,6 +6,10 @@ |
| |
| |
| #include "adreno_gpu.h" |
| +#include "a6xx_enums.xml.h" |
| +#include "a7xx_enums.xml.h" |
| +#include "a6xx_perfcntrs.xml.h" |
| +#include "a7xx_perfcntrs.xml.h" |
| #include "a6xx.xml.h" |
| |
| #include "a6xx_gmu.h" |
| diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |
| index 341a72a67401..a85d3df7a5fa 100644 |
| --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |
| +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |
| @@ -158,7 +158,7 @@ static int a6xx_crashdumper_run(struct msm_gpu *gpu, |
| /* Make sure all pending memory writes are posted */ |
| wmb(); |
| |
| - gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova); |
| + gpu_write64(gpu, REG_A6XX_CP_CRASH_DUMP_SCRIPT_BASE, dumper->iova); |
| |
| gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); |
| |
| diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h |
| index e545106c70be..95d93ac6812a 100644 |
| --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h |
| +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h |
| @@ -212,7 +212,7 @@ static const struct a6xx_shader_block { |
| SHADER(A6XX_SP_LB_5_DATA, 0x200), |
| SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800), |
| SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280), |
| - SHADER(A6XX_SP_UAV_DATA, 0x80), |
| + SHADER(A6XX_SP_GFX_UAV_BASE_DATA, 0x80), |
| SHADER(A6XX_SP_INST_TAG, 0x80), |
| SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80), |
| SHADER(A6XX_SP_TMO_UMO_TAG, 0x80), |
| diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c |
| index 3b17fd2dba89..e6084e6999eb 100644 |
| --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c |
| +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c |
| @@ -210,7 +210,7 @@ void a6xx_preempt_hw_init(struct msm_gpu *gpu) |
| gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0); |
| |
| /* Enable the GMEM save/restore feature for preemption */ |
| - gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x1); |
| + gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1); |
| |
| /* Reset the preemption state */ |
| set_preempt_state(a6xx_gpu, PREEMPT_NONE); |
| diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h |
| index 9a327d543f27..e02cabb39f19 100644 |
| --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h |
| +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h |
| @@ -1311,8 +1311,8 @@ static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { |
| REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000}, |
| { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, |
| REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040}, |
| - { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR, |
| - REG_A7XX_CP_RESOURCE_TBL_DBG_DATA, 0x04100}, |
| + { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR, |
| + REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA, 0x04100}, |
| { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, |
| REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200}, |
| { "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR, |
| diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml |
| index 2db425abf0f3..d860fd94feae 100644 |
| --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml |
| +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml |
| @@ -5,6 +5,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| <import file="freedreno_copyright.xml"/> |
| <import file="adreno/adreno_common.xml"/> |
| <import file="adreno/adreno_pm4.xml"/> |
| +<import file="adreno/a6xx_enums.xml"/> |
| +<import file="adreno/a7xx_enums.xml"/> |
| +<import file="adreno/a6xx_perfcntrs.xml"/> |
| +<import file="adreno/a7xx_perfcntrs.xml"/> |
| +<import file="adreno/a6xx_descriptors.xml"/> |
| |
| <!-- |
| Each register that is actually being used by driver should have "usage" defined, |
| @@ -20,2205 +25,6 @@ is either overwritten by renderpass/blit (ib2) or not used if not overwritten |
| by a particular renderpass/blit. |
| --> |
| |
| -<!-- these might be same as a5xx --> |
| -<enum name="a6xx_tile_mode"> |
| - <value name="TILE6_LINEAR" value="0"/> |
| - <value name="TILE6_2" value="2"/> |
| - <value name="TILE6_3" value="3"/> |
| -</enum> |
| - |
| -<enum name="a6xx_format"> |
| - <value value="0x02" name="FMT6_A8_UNORM"/> |
| - <value value="0x03" name="FMT6_8_UNORM"/> |
| - <value value="0x04" name="FMT6_8_SNORM"/> |
| - <value value="0x05" name="FMT6_8_UINT"/> |
| - <value value="0x06" name="FMT6_8_SINT"/> |
| - |
| - <value value="0x08" name="FMT6_4_4_4_4_UNORM"/> |
| - <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/> |
| - <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only --> |
| - <value value="0x0e" name="FMT6_5_6_5_UNORM"/> |
| - |
| - <value value="0x0f" name="FMT6_8_8_UNORM"/> |
| - <value value="0x10" name="FMT6_8_8_SNORM"/> |
| - <value value="0x11" name="FMT6_8_8_UINT"/> |
| - <value value="0x12" name="FMT6_8_8_SINT"/> |
| - <value value="0x13" name="FMT6_L8_A8_UNORM"/> |
| - |
| - <value value="0x15" name="FMT6_16_UNORM"/> |
| - <value value="0x16" name="FMT6_16_SNORM"/> |
| - <value value="0x17" name="FMT6_16_FLOAT"/> |
| - <value value="0x18" name="FMT6_16_UINT"/> |
| - <value value="0x19" name="FMT6_16_SINT"/> |
| - |
| - <value value="0x21" name="FMT6_8_8_8_UNORM"/> |
| - <value value="0x22" name="FMT6_8_8_8_SNORM"/> |
| - <value value="0x23" name="FMT6_8_8_8_UINT"/> |
| - <value value="0x24" name="FMT6_8_8_8_SINT"/> |
| - |
| - <value value="0x30" name="FMT6_8_8_8_8_UNORM"/> |
| - <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha --> |
| - <value value="0x32" name="FMT6_8_8_8_8_SNORM"/> |
| - <value value="0x33" name="FMT6_8_8_8_8_UINT"/> |
| - <value value="0x34" name="FMT6_8_8_8_8_SINT"/> |
| - |
| - <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/> |
| - |
| - <value value="0x36" name="FMT6_10_10_10_2_UNORM"/> |
| - <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/> |
| - <value value="0x39" name="FMT6_10_10_10_2_SNORM"/> |
| - <value value="0x3a" name="FMT6_10_10_10_2_UINT"/> |
| - <value value="0x3b" name="FMT6_10_10_10_2_SINT"/> |
| - |
| - <value value="0x42" name="FMT6_11_11_10_FLOAT"/> |
| - |
| - <value value="0x43" name="FMT6_16_16_UNORM"/> |
| - <value value="0x44" name="FMT6_16_16_SNORM"/> |
| - <value value="0x45" name="FMT6_16_16_FLOAT"/> |
| - <value value="0x46" name="FMT6_16_16_UINT"/> |
| - <value value="0x47" name="FMT6_16_16_SINT"/> |
| - |
| - <value value="0x48" name="FMT6_32_UNORM"/> |
| - <value value="0x49" name="FMT6_32_SNORM"/> |
| - <value value="0x4a" name="FMT6_32_FLOAT"/> |
| - <value value="0x4b" name="FMT6_32_UINT"/> |
| - <value value="0x4c" name="FMT6_32_SINT"/> |
| - <value value="0x4d" name="FMT6_32_FIXED"/> |
| - |
| - <value value="0x58" name="FMT6_16_16_16_UNORM"/> |
| - <value value="0x59" name="FMT6_16_16_16_SNORM"/> |
| - <value value="0x5a" name="FMT6_16_16_16_FLOAT"/> |
| - <value value="0x5b" name="FMT6_16_16_16_UINT"/> |
| - <value value="0x5c" name="FMT6_16_16_16_SINT"/> |
| - |
| - <value value="0x60" name="FMT6_16_16_16_16_UNORM"/> |
| - <value value="0x61" name="FMT6_16_16_16_16_SNORM"/> |
| - <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/> |
| - <value value="0x63" name="FMT6_16_16_16_16_UINT"/> |
| - <value value="0x64" name="FMT6_16_16_16_16_SINT"/> |
| - |
| - <value value="0x65" name="FMT6_32_32_UNORM"/> |
| - <value value="0x66" name="FMT6_32_32_SNORM"/> |
| - <value value="0x67" name="FMT6_32_32_FLOAT"/> |
| - <value value="0x68" name="FMT6_32_32_UINT"/> |
| - <value value="0x69" name="FMT6_32_32_SINT"/> |
| - <value value="0x6a" name="FMT6_32_32_FIXED"/> |
| - |
| - <value value="0x70" name="FMT6_32_32_32_UNORM"/> |
| - <value value="0x71" name="FMT6_32_32_32_SNORM"/> |
| - <value value="0x72" name="FMT6_32_32_32_UINT"/> |
| - <value value="0x73" name="FMT6_32_32_32_SINT"/> |
| - <value value="0x74" name="FMT6_32_32_32_FLOAT"/> |
| - <value value="0x75" name="FMT6_32_32_32_FIXED"/> |
| - |
| - <value value="0x80" name="FMT6_32_32_32_32_UNORM"/> |
| - <value value="0x81" name="FMT6_32_32_32_32_SNORM"/> |
| - <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/> |
| - <value value="0x83" name="FMT6_32_32_32_32_UINT"/> |
| - <value value="0x84" name="FMT6_32_32_32_32_SINT"/> |
| - <value value="0x85" name="FMT6_32_32_32_32_FIXED"/> |
| - |
| - <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY --> |
| - <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV --> |
| - <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 --> |
| - <value value="0x8f" name="FMT6_NV21"/> |
| - <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 --> |
| - |
| - <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/> |
| - |
| - <!-- Note: tiling/UBWC for these may be different from equivalent formats |
| - For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM |
| - --> |
| - <value value="0x94" name="FMT6_NV12_Y"/> |
| - <value value="0x95" name="FMT6_NV12_UV"/> |
| - <value value="0x96" name="FMT6_NV12_VU"/> |
| - <value value="0x97" name="FMT6_NV12_4R"/> |
| - <value value="0x98" name="FMT6_NV12_4R_Y"/> |
| - <value value="0x99" name="FMT6_NV12_4R_UV"/> |
| - <value value="0x9a" name="FMT6_P010"/> |
| - <value value="0x9b" name="FMT6_P010_Y"/> |
| - <value value="0x9c" name="FMT6_P010_UV"/> |
| - <value value="0x9d" name="FMT6_TP10"/> |
| - <value value="0x9e" name="FMT6_TP10_Y"/> |
| - <value value="0x9f" name="FMT6_TP10_UV"/> |
| - |
| - <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/> |
| - |
| - <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/> |
| - <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/> |
| - <value value="0xad" name="FMT6_ETC2_R11_UNORM"/> |
| - <value value="0xae" name="FMT6_ETC2_R11_SNORM"/> |
| - <value value="0xaf" name="FMT6_ETC1"/> |
| - <value value="0xb0" name="FMT6_ETC2_RGB8"/> |
| - <value value="0xb1" name="FMT6_ETC2_RGBA8"/> |
| - <value value="0xb2" name="FMT6_ETC2_RGB8A1"/> |
| - <value value="0xb3" name="FMT6_DXT1"/> |
| - <value value="0xb4" name="FMT6_DXT3"/> |
| - <value value="0xb5" name="FMT6_DXT5"/> |
| - <value value="0xb7" name="FMT6_RGTC1_UNORM"/> |
| - <value value="0xb8" name="FMT6_RGTC1_SNORM"/> |
| - <value value="0xbb" name="FMT6_RGTC2_UNORM"/> |
| - <value value="0xbc" name="FMT6_RGTC2_SNORM"/> |
| - <value value="0xbe" name="FMT6_BPTC_UFLOAT"/> |
| - <value value="0xbf" name="FMT6_BPTC_FLOAT"/> |
| - <value value="0xc0" name="FMT6_BPTC"/> |
| - <value value="0xc1" name="FMT6_ASTC_4x4"/> |
| - <value value="0xc2" name="FMT6_ASTC_5x4"/> |
| - <value value="0xc3" name="FMT6_ASTC_5x5"/> |
| - <value value="0xc4" name="FMT6_ASTC_6x5"/> |
| - <value value="0xc5" name="FMT6_ASTC_6x6"/> |
| - <value value="0xc6" name="FMT6_ASTC_8x5"/> |
| - <value value="0xc7" name="FMT6_ASTC_8x6"/> |
| - <value value="0xc8" name="FMT6_ASTC_8x8"/> |
| - <value value="0xc9" name="FMT6_ASTC_10x5"/> |
| - <value value="0xca" name="FMT6_ASTC_10x6"/> |
| - <value value="0xcb" name="FMT6_ASTC_10x8"/> |
| - <value value="0xcc" name="FMT6_ASTC_10x10"/> |
| - <value value="0xcd" name="FMT6_ASTC_12x10"/> |
| - <value value="0xce" name="FMT6_ASTC_12x12"/> |
| - |
| - <!-- for sampling stencil (integer, 2nd channel), not available on a630 --> |
| - <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/> |
| - |
| - <!-- Not a hw enum, used internally in driver --> |
| - <value value="0xff" name="FMT6_NONE"/> |
| - |
| -</enum> |
| - |
| -<!-- probably same as a5xx --> |
| -<enum name="a6xx_polygon_mode"> |
| - <value name="POLYMODE6_POINTS" value="1"/> |
| - <value name="POLYMODE6_LINES" value="2"/> |
| - <value name="POLYMODE6_TRIANGLES" value="3"/> |
| -</enum> |
| - |
| -<enum name="a6xx_depth_format"> |
| - <value name="DEPTH6_NONE" value="0"/> |
| - <value name="DEPTH6_16" value="1"/> |
| - <value name="DEPTH6_24_8" value="2"/> |
| - <value name="DEPTH6_32" value="4"/> |
| -</enum> |
| - |
| -<bitset name="a6x_cp_protect" inline="yes"> |
| - <bitfield name="BASE_ADDR" low="0" high="17"/> |
| - <bitfield name="MASK_LEN" low="18" high="30"/> |
| - <bitfield name="READ" pos="31" type="boolean"/> |
| -</bitset> |
| - |
| -<enum name="a6xx_shader_id"> |
| - <value value="0x9" name="A6XX_TP0_TMO_DATA"/> |
| - <value value="0xa" name="A6XX_TP0_SMO_DATA"/> |
| - <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/> |
| - <value value="0x19" name="A6XX_TP1_TMO_DATA"/> |
| - <value value="0x1a" name="A6XX_TP1_SMO_DATA"/> |
| - <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/> |
| - <value value="0x29" name="A6XX_SP_INST_DATA"/> |
| - <value value="0x2a" name="A6XX_SP_LB_0_DATA"/> |
| - <value value="0x2b" name="A6XX_SP_LB_1_DATA"/> |
| - <value value="0x2c" name="A6XX_SP_LB_2_DATA"/> |
| - <value value="0x2d" name="A6XX_SP_LB_3_DATA"/> |
| - <value value="0x2e" name="A6XX_SP_LB_4_DATA"/> |
| - <value value="0x2f" name="A6XX_SP_LB_5_DATA"/> |
| - <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/> |
| - <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/> |
| - <value value="0x32" name="A6XX_SP_UAV_DATA"/> |
| - <value value="0x33" name="A6XX_SP_INST_TAG"/> |
| - <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/> |
| - <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/> |
| - <value value="0x36" name="A6XX_SP_SMO_TAG"/> |
| - <value value="0x37" name="A6XX_SP_STATE_DATA"/> |
| - <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/> |
| - <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/> |
| - <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/> |
| - <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/> |
| - <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> |
| - <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> |
| - <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/> |
| - <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/> |
| - <value value="0x52" name="A6XX_HLSQ_INST_RAM"/> |
| - <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/> |
| - <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/> |
| - <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/> |
| - <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/> |
| - <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/> |
| - <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> |
| - <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> |
| - <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/> |
| - <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/> |
| - <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/> |
| - <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/> |
| - <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/> |
| - <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/> |
| - <value value="0x70" name="A6XX_SP_LB_6_DATA"/> |
| - <value value="0x71" name="A6XX_SP_LB_7_DATA"/> |
| - <value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/> |
| -</enum> |
| - |
| -<enum name="a7xx_statetype_id"> |
| - <value value="0" name="A7XX_TP0_NCTX_REG"/> |
| - <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/> |
| - <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/> |
| - <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/> |
| - <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/> |
| - <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/> |
| - <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/> |
| - <value value="9" name="A7XX_TP0_TMO_DATA"/> |
| - <value value="10" name="A7XX_TP0_SMO_DATA"/> |
| - <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/> |
| - <value value="32" name="A7XX_SP_NCTX_REG"/> |
| - <value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/> |
| - <value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/> |
| - <value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/> |
| - <value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/> |
| - <value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/> |
| - <value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/> |
| - <value value="39" name="A7XX_SP_INST_DATA"/> |
| - <value value="40" name="A7XX_SP_INST_DATA_1"/> |
| - <value value="41" name="A7XX_SP_LB_0_DATA"/> |
| - <value value="42" name="A7XX_SP_LB_1_DATA"/> |
| - <value value="43" name="A7XX_SP_LB_2_DATA"/> |
| - <value value="44" name="A7XX_SP_LB_3_DATA"/> |
| - <value value="45" name="A7XX_SP_LB_4_DATA"/> |
| - <value value="46" name="A7XX_SP_LB_5_DATA"/> |
| - <value value="47" name="A7XX_SP_LB_6_DATA"/> |
| - <value value="48" name="A7XX_SP_LB_7_DATA"/> |
| - <value value="49" name="A7XX_SP_CB_RAM"/> |
| - <value value="50" name="A7XX_SP_LB_13_DATA"/> |
| - <value value="51" name="A7XX_SP_LB_14_DATA"/> |
| - <value value="52" name="A7XX_SP_INST_TAG"/> |
| - <value value="53" name="A7XX_SP_INST_DATA_2"/> |
| - <value value="54" name="A7XX_SP_TMO_TAG"/> |
| - <value value="55" name="A7XX_SP_SMO_TAG"/> |
| - <value value="56" name="A7XX_SP_STATE_DATA"/> |
| - <value value="57" name="A7XX_SP_HWAVE_RAM"/> |
| - <value value="58" name="A7XX_SP_L0_INST_BUF"/> |
| - <value value="59" name="A7XX_SP_LB_8_DATA"/> |
| - <value value="60" name="A7XX_SP_LB_9_DATA"/> |
| - <value value="61" name="A7XX_SP_LB_10_DATA"/> |
| - <value value="62" name="A7XX_SP_LB_11_DATA"/> |
| - <value value="63" name="A7XX_SP_LB_12_DATA"/> |
| - <value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/> |
| - <value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/> |
| - <value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/> |
| - <value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/> |
| - <value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/> |
| - <value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/> |
| - <value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/> |
| - <value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/> |
| - <value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/> |
| - <value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/> |
| - <value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/> |
| - <value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> |
| - <value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> |
| - <value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/> |
| - <value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/> |
| - <value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/> |
| - <value value="82" name="A7XX_HLSQ_INST_RAM"/> |
| - <value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/> |
| - <value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/> |
| - <value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/> |
| - <value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/> |
| - <value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/> |
| - <value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> |
| - <value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> |
| - <value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/> |
| - <value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/> |
| - <value value="92" name="A7XX_HLSQ_INST_RAM_1"/> |
| - <value value="93" name="A7XX_HLSQ_STPROC_META"/> |
| - <value value="94" name="A7XX_HLSQ_BV_BE_META"/> |
| - <value value="95" name="A7XX_HLSQ_INST_RAM_2"/> |
| - <value value="96" name="A7XX_HLSQ_DATAPATH_META"/> |
| - <value value="97" name="A7XX_HLSQ_FRONTEND_META"/> |
| - <value value="98" name="A7XX_HLSQ_INDIRECT_META"/> |
| - <value value="99" name="A7XX_HLSQ_BACKEND_META"/> |
| -</enum> |
| - |
| -<enum name="a6xx_debugbus_id"> |
| - <value value="0x1" name="A6XX_DBGBUS_CP"/> |
| - <value value="0x2" name="A6XX_DBGBUS_RBBM"/> |
| - <value value="0x3" name="A6XX_DBGBUS_VBIF"/> |
| - <value value="0x4" name="A6XX_DBGBUS_HLSQ"/> |
| - <value value="0x5" name="A6XX_DBGBUS_UCHE"/> |
| - <value value="0x6" name="A6XX_DBGBUS_DPM"/> |
| - <value value="0x7" name="A6XX_DBGBUS_TESS"/> |
| - <value value="0x8" name="A6XX_DBGBUS_PC"/> |
| - <value value="0x9" name="A6XX_DBGBUS_VFDP"/> |
| - <value value="0xa" name="A6XX_DBGBUS_VPC"/> |
| - <value value="0xb" name="A6XX_DBGBUS_TSE"/> |
| - <value value="0xc" name="A6XX_DBGBUS_RAS"/> |
| - <value value="0xd" name="A6XX_DBGBUS_VSC"/> |
| - <value value="0xe" name="A6XX_DBGBUS_COM"/> |
| - <value value="0x10" name="A6XX_DBGBUS_LRZ"/> |
| - <value value="0x11" name="A6XX_DBGBUS_A2D"/> |
| - <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/> |
| - <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/> |
| - <value value="0x14" name="A6XX_DBGBUS_RBP"/> |
| - <value value="0x15" name="A6XX_DBGBUS_DCS"/> |
| - <value value="0x16" name="A6XX_DBGBUS_DBGC"/> |
| - <value value="0x17" name="A6XX_DBGBUS_CX"/> |
| - <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/> |
| - <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/> |
| - <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/> |
| - <value value="0x1d" name="A6XX_DBGBUS_GPC"/> |
| - <value value="0x1e" name="A6XX_DBGBUS_LARC"/> |
| - <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/> |
| - <value value="0x20" name="A6XX_DBGBUS_RB_0"/> |
| - <value value="0x21" name="A6XX_DBGBUS_RB_1"/> |
| - <value value="0x22" name="A6XX_DBGBUS_RB_2"/> |
| - <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/> |
| - <value value="0x28" name="A6XX_DBGBUS_CCU_0"/> |
| - <value value="0x29" name="A6XX_DBGBUS_CCU_1"/> |
| - <value value="0x2a" name="A6XX_DBGBUS_CCU_2"/> |
| - <value value="0x38" name="A6XX_DBGBUS_VFD_0"/> |
| - <value value="0x39" name="A6XX_DBGBUS_VFD_1"/> |
| - <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/> |
| - <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/> |
| - <value value="0x3c" name="A6XX_DBGBUS_VFD_4"/> |
| - <value value="0x3d" name="A6XX_DBGBUS_VFD_5"/> |
| - <value value="0x40" name="A6XX_DBGBUS_SP_0"/> |
| - <value value="0x41" name="A6XX_DBGBUS_SP_1"/> |
| - <value value="0x42" name="A6XX_DBGBUS_SP_2"/> |
| - <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/> |
| - <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/> |
| - <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/> |
| - <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/> |
| - <value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/> |
| - <value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/> |
| - <value value="0x58" name="A6XX_DBGBUS_SPTP_0"/> |
| - <value value="0x59" name="A6XX_DBGBUS_SPTP_1"/> |
| - <value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/> |
| - <value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/> |
| - <value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/> |
| - <value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/> |
| -</enum> |
| - |
| -<enum name="a7xx_state_location"> |
| - <value value="0" name="A7XX_HLSQ_STATE"/> |
| - <value value="1" name="A7XX_HLSQ_DP"/> |
| - <value value="2" name="A7XX_SP_TOP"/> |
| - <value value="3" name="A7XX_USPTP"/> |
| - <value value="4" name="A7XX_HLSQ_DP_STR"/> |
| -</enum> |
| - |
| -<enum name="a7xx_pipe"> |
| - <value value="0" name="A7XX_PIPE_NONE"/> |
| - <value value="1" name="A7XX_PIPE_BR"/> |
| - <value value="2" name="A7XX_PIPE_BV"/> |
| - <value value="3" name="A7XX_PIPE_LPAC"/> |
| -</enum> |
| - |
| -<enum name="a7xx_cluster"> |
| - <value value="0" name="A7XX_CLUSTER_NONE"/> |
| - <value value="1" name="A7XX_CLUSTER_FE"/> |
| - <value value="2" name="A7XX_CLUSTER_SP_VS"/> |
| - <value value="3" name="A7XX_CLUSTER_PC_VS"/> |
| - <value value="4" name="A7XX_CLUSTER_GRAS"/> |
| - <value value="5" name="A7XX_CLUSTER_SP_PS"/> |
| - <value value="6" name="A7XX_CLUSTER_VPC_PS"/> |
| - <value value="7" name="A7XX_CLUSTER_PS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_debugbus_id"> |
| - <value value="1" name="A7XX_DBGBUS_CP_0_0"/> |
| - <value value="2" name="A7XX_DBGBUS_CP_0_1"/> |
| - <value value="3" name="A7XX_DBGBUS_RBBM"/> |
| - <value value="5" name="A7XX_DBGBUS_GBIF_GX"/> |
| - <value value="6" name="A7XX_DBGBUS_GBIF_CX"/> |
| - <value value="7" name="A7XX_DBGBUS_HLSQ"/> |
| - <value value="9" name="A7XX_DBGBUS_UCHE_0"/> |
| - <value value="10" name="A7XX_DBGBUS_UCHE_1"/> |
| - <value value="13" name="A7XX_DBGBUS_TESS_BR"/> |
| - <value value="14" name="A7XX_DBGBUS_TESS_BV"/> |
| - <value value="17" name="A7XX_DBGBUS_PC_BR"/> |
| - <value value="18" name="A7XX_DBGBUS_PC_BV"/> |
| - <value value="21" name="A7XX_DBGBUS_VFDP_BR"/> |
| - <value value="22" name="A7XX_DBGBUS_VFDP_BV"/> |
| - <value value="25" name="A7XX_DBGBUS_VPC_BR"/> |
| - <value value="26" name="A7XX_DBGBUS_VPC_BV"/> |
| - <value value="29" name="A7XX_DBGBUS_TSE_BR"/> |
| - <value value="30" name="A7XX_DBGBUS_TSE_BV"/> |
| - <value value="33" name="A7XX_DBGBUS_RAS_BR"/> |
| - <value value="34" name="A7XX_DBGBUS_RAS_BV"/> |
| - <value value="37" name="A7XX_DBGBUS_VSC"/> |
| - <value value="39" name="A7XX_DBGBUS_COM_0"/> |
| - <value value="43" name="A7XX_DBGBUS_LRZ_BR"/> |
| - <value value="44" name="A7XX_DBGBUS_LRZ_BV"/> |
| - <value value="47" name="A7XX_DBGBUS_UFC_0"/> |
| - <value value="48" name="A7XX_DBGBUS_UFC_1"/> |
| - <value value="55" name="A7XX_DBGBUS_GMU_GX"/> |
| - <value value="59" name="A7XX_DBGBUS_DBGC"/> |
| - <value value="60" name="A7XX_DBGBUS_CX"/> |
| - <value value="61" name="A7XX_DBGBUS_GMU_CX"/> |
| - <value value="62" name="A7XX_DBGBUS_GPC_BR"/> |
| - <value value="63" name="A7XX_DBGBUS_GPC_BV"/> |
| - <value value="66" name="A7XX_DBGBUS_LARC"/> |
| - <value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/> |
| - <value value="70" name="A7XX_DBGBUS_RB_0"/> |
| - <value value="71" name="A7XX_DBGBUS_RB_1"/> |
| - <value value="72" name="A7XX_DBGBUS_RB_2"/> |
| - <value value="73" name="A7XX_DBGBUS_RB_3"/> |
| - <value value="74" name="A7XX_DBGBUS_RB_4"/> |
| - <value value="75" name="A7XX_DBGBUS_RB_5"/> |
| - <value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/> |
| - <value value="106" name="A7XX_DBGBUS_CCU_0"/> |
| - <value value="107" name="A7XX_DBGBUS_CCU_1"/> |
| - <value value="108" name="A7XX_DBGBUS_CCU_2"/> |
| - <value value="109" name="A7XX_DBGBUS_CCU_3"/> |
| - <value value="110" name="A7XX_DBGBUS_CCU_4"/> |
| - <value value="111" name="A7XX_DBGBUS_CCU_5"/> |
| - <value value="138" name="A7XX_DBGBUS_VFD_BR_0"/> |
| - <value value="139" name="A7XX_DBGBUS_VFD_BR_1"/> |
| - <value value="140" name="A7XX_DBGBUS_VFD_BR_2"/> |
| - <value value="141" name="A7XX_DBGBUS_VFD_BR_3"/> |
| - <value value="142" name="A7XX_DBGBUS_VFD_BR_4"/> |
| - <value value="143" name="A7XX_DBGBUS_VFD_BR_5"/> |
| - <value value="144" name="A7XX_DBGBUS_VFD_BR_6"/> |
| - <value value="145" name="A7XX_DBGBUS_VFD_BR_7"/> |
| - <value value="202" name="A7XX_DBGBUS_VFD_BV_0"/> |
| - <value value="203" name="A7XX_DBGBUS_VFD_BV_1"/> |
| - <value value="204" name="A7XX_DBGBUS_VFD_BV_2"/> |
| - <value value="205" name="A7XX_DBGBUS_VFD_BV_3"/> |
| - <value value="234" name="A7XX_DBGBUS_USP_0"/> |
| - <value value="235" name="A7XX_DBGBUS_USP_1"/> |
| - <value value="236" name="A7XX_DBGBUS_USP_2"/> |
| - <value value="237" name="A7XX_DBGBUS_USP_3"/> |
| - <value value="238" name="A7XX_DBGBUS_USP_4"/> |
| - <value value="239" name="A7XX_DBGBUS_USP_5"/> |
| - <value value="266" name="A7XX_DBGBUS_TP_0"/> |
| - <value value="267" name="A7XX_DBGBUS_TP_1"/> |
| - <value value="268" name="A7XX_DBGBUS_TP_2"/> |
| - <value value="269" name="A7XX_DBGBUS_TP_3"/> |
| - <value value="270" name="A7XX_DBGBUS_TP_4"/> |
| - <value value="271" name="A7XX_DBGBUS_TP_5"/> |
| - <value value="272" name="A7XX_DBGBUS_TP_6"/> |
| - <value value="273" name="A7XX_DBGBUS_TP_7"/> |
| - <value value="274" name="A7XX_DBGBUS_TP_8"/> |
| - <value value="275" name="A7XX_DBGBUS_TP_9"/> |
| - <value value="276" name="A7XX_DBGBUS_TP_10"/> |
| - <value value="277" name="A7XX_DBGBUS_TP_11"/> |
| - <value value="330" name="A7XX_DBGBUS_USPTP_0"/> |
| - <value value="331" name="A7XX_DBGBUS_USPTP_1"/> |
| - <value value="332" name="A7XX_DBGBUS_USPTP_2"/> |
| - <value value="333" name="A7XX_DBGBUS_USPTP_3"/> |
| - <value value="334" name="A7XX_DBGBUS_USPTP_4"/> |
| - <value value="335" name="A7XX_DBGBUS_USPTP_5"/> |
| - <value value="336" name="A7XX_DBGBUS_USPTP_6"/> |
| - <value value="337" name="A7XX_DBGBUS_USPTP_7"/> |
| - <value value="338" name="A7XX_DBGBUS_USPTP_8"/> |
| - <value value="339" name="A7XX_DBGBUS_USPTP_9"/> |
| - <value value="340" name="A7XX_DBGBUS_USPTP_10"/> |
| - <value value="341" name="A7XX_DBGBUS_USPTP_11"/> |
| - <value value="396" name="A7XX_DBGBUS_CCHE_0"/> |
| - <value value="397" name="A7XX_DBGBUS_CCHE_1"/> |
| - <value value="398" name="A7XX_DBGBUS_CCHE_2"/> |
| - <value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/> |
| - <value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/> |
| - <value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/> |
| - <value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/> |
| - <value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/> |
| - <value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/> |
| - <value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/> |
| - <value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/> |
| - <value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/> |
| - <value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/> |
| - <value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/> |
| - <value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/> |
| - <value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/> |
| - <value value="447" name="A7XX_DBGBUS_CGC_CORE"/> |
| -</enum> |
| - |
| -<enum name="a6xx_cp_perfcounter_select"> |
| - <value value="0" name="PERF_CP_ALWAYS_COUNT"/> |
| - <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> |
| - <value value="2" name="PERF_CP_BUSY_CYCLES"/> |
| - <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> |
| - <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> |
| - <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> |
| - <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> |
| - <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> |
| - <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> |
| - <value value="9" name="PERF_CP_MODE_SWITCH"/> |
| - <value value="10" name="PERF_CP_ZPASS_DONE"/> |
| - <value value="11" name="PERF_CP_CONTEXT_DONE"/> |
| - <value value="12" name="PERF_CP_CACHE_FLUSH"/> |
| - <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> |
| - <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> |
| - <value value="15" name="PERF_CP_SQE_IDLE"/> |
| - <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> |
| - <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> |
| - <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> |
| - <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> |
| - <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> |
| - <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> |
| - <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> |
| - <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> |
| - <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> |
| - <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> |
| - <value value="26" name="PERF_CP_SQE_T4_EXEC"/> |
| - <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> |
| - <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> |
| - <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> |
| - <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> |
| - <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> |
| - <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> |
| - <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> |
| - <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> |
| - <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> |
| - <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> |
| - <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> |
| - <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> |
| - <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> |
| - <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> |
| - <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> |
| - <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> |
| - <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> |
| - <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> |
| - <value value="45" name="PERF_CP_PM4_DATA"/> |
| - <value value="46" name="PERF_CP_PM4_HEADERS"/> |
| - <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> |
| - <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> |
| - <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> |
| -</enum> |
| - |
| -<enum name="a6xx_rbbm_perfcounter_select"> |
| - <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> |
| - <value value="1" name="PERF_RBBM_ALWAYS_ON"/> |
| - <value value="2" name="PERF_RBBM_TSE_BUSY"/> |
| - <value value="3" name="PERF_RBBM_RAS_BUSY"/> |
| - <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> |
| - <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> |
| - <value value="6" name="PERF_RBBM_STATUS_MASKED"/> |
| - <value value="7" name="PERF_RBBM_COM_BUSY"/> |
| - <value value="8" name="PERF_RBBM_DCOM_BUSY"/> |
| - <value value="9" name="PERF_RBBM_VBIF_BUSY"/> |
| - <value value="10" name="PERF_RBBM_VSC_BUSY"/> |
| - <value value="11" name="PERF_RBBM_TESS_BUSY"/> |
| - <value value="12" name="PERF_RBBM_UCHE_BUSY"/> |
| - <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> |
| -</enum> |
| - |
| -<enum name="a6xx_pc_perfcounter_select"> |
| - <value value="0" name="PERF_PC_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_PC_WORKING_CYCLES"/> |
| - <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> |
| - <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> |
| - <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> |
| - <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> |
| - <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> |
| - <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> |
| - <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> |
| - <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> |
| - <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> |
| - <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> |
| - <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> |
| - <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> |
| - <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> |
| - <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> |
| - <value value="16" name="PERF_PC_INSTANCES"/> |
| - <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> |
| - <value value="18" name="PERF_PC_DEAD_PRIM"/> |
| - <value value="19" name="PERF_PC_LIVE_PRIM"/> |
| - <value value="20" name="PERF_PC_VERTEX_HITS"/> |
| - <value value="21" name="PERF_PC_IA_VERTICES"/> |
| - <value value="22" name="PERF_PC_IA_PRIMITIVES"/> |
| - <value value="23" name="PERF_PC_GS_PRIMITIVES"/> |
| - <value value="24" name="PERF_PC_HS_INVOCATIONS"/> |
| - <value value="25" name="PERF_PC_DS_INVOCATIONS"/> |
| - <value value="26" name="PERF_PC_VS_INVOCATIONS"/> |
| - <value value="27" name="PERF_PC_GS_INVOCATIONS"/> |
| - <value value="28" name="PERF_PC_DS_PRIMITIVES"/> |
| - <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> |
| - <value value="30" name="PERF_PC_3D_DRAWCALLS"/> |
| - <value value="31" name="PERF_PC_2D_DRAWCALLS"/> |
| - <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> |
| - <value value="33" name="PERF_TESS_BUSY_CYCLES"/> |
| - <value value="34" name="PERF_TESS_WORKING_CYCLES"/> |
| - <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> |
| - <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> |
| - <value value="37" name="PERF_PC_TSE_TRANSACTION"/> |
| - <value value="38" name="PERF_PC_TSE_VERTEX"/> |
| - <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> |
| - <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> |
| - <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> |
| -</enum> |
| - |
| -<enum name="a6xx_vfd_perfcounter_select"> |
| - <value value="0" name="PERF_VFD_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> |
| - <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> |
| - <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> |
| - <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> |
| - <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> |
| - <value value="6" name="PERF_VFD_RBUFFER_FULL"/> |
| - <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> |
| - <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> |
| - <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> |
| - <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> |
| - <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> |
| - <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> |
| - <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> |
| - <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> |
| - <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> |
| - <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> |
| - <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> |
| - <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> |
| - <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> |
| - <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> |
| - <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> |
| - <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> |
| -</enum> |
| - |
| -<enum name="a6xx_hlsq_perfcounter_select"> |
| - <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> |
| - <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> |
| - <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> |
| - <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> |
| - <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> |
| - <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> |
| - <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> |
| - <value value="8" name="PERF_HLSQ_QUADS"/> |
| - <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> |
| - <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> |
| - <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> |
| - <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> |
| - <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> |
| - <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> |
| - <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> |
| - <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> |
| - <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> |
| - <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> |
| - <value value="19" name="PERF_HLSQ_PIXELS"/> |
| - <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> |
| -</enum> |
| - |
| -<enum name="a6xx_vpc_perfcounter_select"> |
| - <value value="0" name="PERF_VPC_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_VPC_WORKING_CYCLES"/> |
| - <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> |
| - <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> |
| - <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> |
| - <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> |
| - <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> |
| - <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> |
| - <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> |
| - <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> |
| - <value value="10" name="PERF_VPC_SP_COMPONENTS"/> |
| - <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> |
| - <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> |
| - <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> |
| - <value value="14" name="PERF_VPC_LM_TRANSACTION"/> |
| - <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> |
| - <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> |
| - <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> |
| - <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> |
| - <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> |
| - <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> |
| - <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> |
| - <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> |
| - <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> |
| - <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> |
| - <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> |
| - <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> |
| - <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> |
| -</enum> |
| - |
| -<enum name="a6xx_tse_perfcounter_select"> |
| - <value value="0" name="PERF_TSE_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> |
| - <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> |
| - <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> |
| - <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> |
| - <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> |
| - <value value="6" name="PERF_TSE_INPUT_PRIM"/> |
| - <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> |
| - <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> |
| - <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> |
| - <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> |
| - <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> |
| - <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> |
| - <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> |
| - <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> |
| - <value value="15" name="PERF_TSE_CINVOCATION"/> |
| - <value value="16" name="PERF_TSE_CPRIMITIVES"/> |
| - <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> |
| - <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> |
| - <value value="19" name="PERF_TSE_CLIP_PLANES"/> |
| -</enum> |
| - |
| -<enum name="a6xx_ras_perfcounter_select"> |
| - <value value="0" name="PERF_RAS_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> |
| - <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> |
| - <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> |
| - <value value="4" name="PERF_RAS_SUPER_TILES"/> |
| - <value value="5" name="PERF_RAS_8X4_TILES"/> |
| - <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> |
| - <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> |
| - <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> |
| - <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> |
| - <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> |
| - <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> |
| - <value value="12" name="PERF_RAS_BLOCKS"/> |
| -</enum> |
| - |
| -<enum name="a6xx_uche_perfcounter_select"> |
| - <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> |
| - <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> |
| - <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> |
| - <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> |
| - <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> |
| - <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> |
| - <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> |
| - <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> |
| - <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> |
| - <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> |
| - <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> |
| - <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> |
| - <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> |
| - <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> |
| - <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> |
| - <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> |
| - <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> |
| - <value value="18" name="PERF_UCHE_EVICTS"/> |
| - <value value="19" name="PERF_UCHE_BANK_REQ0"/> |
| - <value value="20" name="PERF_UCHE_BANK_REQ1"/> |
| - <value value="21" name="PERF_UCHE_BANK_REQ2"/> |
| - <value value="22" name="PERF_UCHE_BANK_REQ3"/> |
| - <value value="23" name="PERF_UCHE_BANK_REQ4"/> |
| - <value value="24" name="PERF_UCHE_BANK_REQ5"/> |
| - <value value="25" name="PERF_UCHE_BANK_REQ6"/> |
| - <value value="26" name="PERF_UCHE_BANK_REQ7"/> |
| - <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> |
| - <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> |
| - <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> |
| - <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> |
| - <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> |
| - <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> |
| - <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> |
| - <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> |
| - <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> |
| - <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> |
| - <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> |
| - <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> |
| - <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> |
| -</enum> |
| - |
| -<enum name="a6xx_tp_perfcounter_select"> |
| - <value value="0" name="PERF_TP_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> |
| - <value value="2" name="PERF_TP_LATENCY_CYCLES"/> |
| - <value value="3" name="PERF_TP_LATENCY_TRANS"/> |
| - <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> |
| - <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> |
| - <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> |
| - <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> |
| - <value value="8" name="PERF_TP_SP_TP_TRANS"/> |
| - <value value="9" name="PERF_TP_TP_SP_TRANS"/> |
| - <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> |
| - <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> |
| - <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> |
| - <value value="13" name="PERF_TP_QUADS_RECEIVED"/> |
| - <value value="14" name="PERF_TP_QUADS_OFFSET"/> |
| - <value value="15" name="PERF_TP_QUADS_SHADOW"/> |
| - <value value="16" name="PERF_TP_QUADS_ARRAY"/> |
| - <value value="17" name="PERF_TP_QUADS_GRADIENT"/> |
| - <value value="18" name="PERF_TP_QUADS_1D"/> |
| - <value value="19" name="PERF_TP_QUADS_2D"/> |
| - <value value="20" name="PERF_TP_QUADS_BUFFER"/> |
| - <value value="21" name="PERF_TP_QUADS_3D"/> |
| - <value value="22" name="PERF_TP_QUADS_CUBE"/> |
| - <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> |
| - <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> |
| - <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> |
| - <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> |
| - <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> |
| - <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> |
| - <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> |
| - <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> |
| - <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> |
| - <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> |
| - <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> |
| - <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> |
| - <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> |
| - <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> |
| - <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> |
| - <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> |
| - <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> |
| - <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> |
| - <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> |
| - <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> |
| - <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> |
| - <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> |
| - <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> |
| - <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> |
| - <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> |
| - <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> |
| - <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> |
| - <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> |
| - <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> |
| - <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> |
| - <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> |
| - <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> |
| - <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> |
| - <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> |
| -</enum> |
| - |
| -<enum name="a6xx_sp_perfcounter_select"> |
| - <value value="0" name="PERF_SP_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> |
| - <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> |
| - <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> |
| - <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> |
| - <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> |
| - <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> |
| - <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> |
| - <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> |
| - <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> |
| - <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> |
| - <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> |
| - <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> |
| - <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> |
| - <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> |
| - <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> |
| - <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> |
| - <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> |
| - <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> |
| - <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> |
| - <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> |
| - <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> |
| - <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> |
| - <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> |
| - <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> |
| - <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> |
| - <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> |
| - <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> |
| - <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> |
| - <value value="29" name="PERF_SP_LM_ATOMICS"/> |
| - <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> |
| - <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> |
| - <value value="32" name="PERF_SP_GM_ATOMICS"/> |
| - <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> |
| - <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> |
| - <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| - <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| - <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> |
| - <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> |
| - <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> |
| - <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| - <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| - <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> |
| - <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> |
| - <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> |
| - <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> |
| - <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> |
| - <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> |
| - <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> |
| - <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> |
| - <value value="50" name="PERF_SP_PIXELS_KILLED"/> |
| - <value value="51" name="PERF_SP_ICL1_REQUESTS"/> |
| - <value value="52" name="PERF_SP_ICL1_MISSES"/> |
| - <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> |
| - <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> |
| - <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> |
| - <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> |
| - <value value="57" name="PERF_SP_GPR_READ"/> |
| - <value value="58" name="PERF_SP_GPR_WRITE"/> |
| - <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| - <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| - <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> |
| - <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> |
| - <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> |
| - <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> |
| - <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> |
| - <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> |
| - <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> |
| - <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> |
| - <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> |
| - <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> |
| - <value value="71" name="PERF_SP_WORKING_EU"/> |
| - <value value="72" name="PERF_SP_ANY_EU_WORKING"/> |
| - <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> |
| - <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> |
| - <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> |
| - <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> |
| - <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> |
| - <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> |
| - <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> |
| - <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> |
| - <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> |
| - <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> |
| - <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> |
| - <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> |
| -</enum> |
| - |
| -<enum name="a6xx_rb_perfcounter_select"> |
| - <value value="0" name="PERF_RB_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> |
| - <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> |
| - <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> |
| - <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> |
| - <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> |
| - <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> |
| - <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> |
| - <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> |
| - <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> |
| - <value value="10" name="PERF_RB_Z_WORKLOAD"/> |
| - <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> |
| - <value value="12" name="PERF_RB_Z_READ"/> |
| - <value value="13" name="PERF_RB_Z_WRITE"/> |
| - <value value="14" name="PERF_RB_C_READ"/> |
| - <value value="15" name="PERF_RB_C_WRITE"/> |
| - <value value="16" name="PERF_RB_TOTAL_PASS"/> |
| - <value value="17" name="PERF_RB_Z_PASS"/> |
| - <value value="18" name="PERF_RB_Z_FAIL"/> |
| - <value value="19" name="PERF_RB_S_FAIL"/> |
| - <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> |
| - <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> |
| - <value value="22" name="PERF_RB_PS_INVOCATIONS"/> |
| - <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> |
| - <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> |
| - <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> |
| - <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> |
| - <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> |
| - <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> |
| - <value value="29" name="PERF_RB_3D_PIXELS"/> |
| - <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> |
| - <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> |
| - <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> |
| - <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> |
| - <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> |
| - <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> |
| - <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> |
| - <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> |
| - <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> |
| - <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> |
| - <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> |
| - <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> |
| - <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> |
| - <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> |
| - <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> |
| - <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> |
| - <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> |
| - <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> |
| -</enum> |
| - |
| -<enum name="a6xx_vsc_perfcounter_select"> |
| - <value value="0" name="PERF_VSC_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_VSC_WORKING_CYCLES"/> |
| - <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> |
| - <value value="3" name="PERF_VSC_EOT_NUM"/> |
| - <value value="4" name="PERF_VSC_INPUT_TILES"/> |
| -</enum> |
| - |
| -<enum name="a6xx_ccu_perfcounter_select"> |
| - <value value="0" name="PERF_CCU_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> |
| - <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> |
| - <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> |
| - <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> |
| - <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> |
| - <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> |
| - <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> |
| - <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> |
| - <value value="9" name="PERF_CCU_GMEM_READ"/> |
| - <value value="10" name="PERF_CCU_GMEM_WRITE"/> |
| - <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> |
| - <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> |
| - <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> |
| - <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> |
| - <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> |
| - <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> |
| - <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> |
| - <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> |
| - <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> |
| - <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> |
| - <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> |
| - <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> |
| - <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> |
| - <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> |
| - <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> |
| - <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> |
| - <value value="27" name="PERF_CCU_2D_RD_REQ"/> |
| - <value value="28" name="PERF_CCU_2D_WR_REQ"/> |
| -</enum> |
| - |
| -<enum name="a6xx_lrz_perfcounter_select"> |
| - <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> |
| - <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> |
| - <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> |
| - <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> |
| - <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> |
| - <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> |
| - <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> |
| - <value value="7" name="PERF_LRZ_LRZ_READ"/> |
| - <value value="8" name="PERF_LRZ_LRZ_WRITE"/> |
| - <value value="9" name="PERF_LRZ_READ_LATENCY"/> |
| - <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> |
| - <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> |
| - <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> |
| - <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> |
| - <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> |
| - <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> |
| - <value value="16" name="PERF_LRZ_TILE_KILLED"/> |
| - <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> |
| - <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> |
| - <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> |
| - <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> |
| - <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> |
| - <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> |
| - <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> |
| - <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> |
| - <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> |
| - <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> |
| - <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> |
| -</enum> |
| - |
| -<enum name="a6xx_cmp_perfcounter_select"> |
| - <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> |
| - <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> |
| - <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> |
| - <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> |
| - <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> |
| - <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> |
| - <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> |
| - <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> |
| - <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> |
| - <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> |
| - <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> |
| - <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> |
| - <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> |
| - <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> |
| - <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> |
| - <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> |
| - <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> |
| - <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> |
| - <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> |
| - <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> |
| - <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> |
| - <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> |
| - <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> |
| - <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> |
| - <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> |
| - <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> |
| - <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> |
| - <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> |
| - <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> |
| - <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> |
| - <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> |
| - <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> |
| - <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> |
| - <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> |
| - <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> |
| - <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> |
| - <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> |
| - <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> |
| - <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> |
| - <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> |
| -</enum> |
| - |
| -<!-- |
| -Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the |
| -component type/size, so I think it relates to internal format used for |
| -blending? The one exception is that 16b unorm and 32b float use the |
| -same value... maybe 16b unorm is uncommon enough that it was just easier |
| -to upconvert to 32b float internally? |
| - |
| - 8b unorm: 10 (sometimes 0, is the high bit part of something else?) |
| -16b unorm: 4 |
| - |
| -32b int: 7 |
| -16b int: 6 |
| - 8b int: 5 |
| - |
| -32b float: 4 |
| -16b float: 3 |
| - --> |
| -<enum name="a6xx_2d_ifmt"> |
| - <value value="0x10" name="R2D_UNORM8"/> |
| - <value value="0x7" name="R2D_INT32"/> |
| - <value value="0x6" name="R2D_INT16"/> |
| - <value value="0x5" name="R2D_INT8"/> |
| - <value value="0x4" name="R2D_FLOAT32"/> |
| - <value value="0x3" name="R2D_FLOAT16"/> |
| - <value value="0x1" name="R2D_UNORM8_SRGB"/> |
| - <value value="0x0" name="R2D_RAW"/> |
| -</enum> |
| - |
| -<enum name="a6xx_ztest_mode"> |
| - <doc>Allow early z-test and early-lrz (if applicable)</doc> |
| - <value value="0x0" name="A6XX_EARLY_Z"/> |
| - <doc>Disable early z-test and early-lrz test (if applicable)</doc> |
| - <value value="0x1" name="A6XX_LATE_Z"/> |
| - <doc> |
| - A special mode that allows early-lrz test but disables |
| - early-z test. Which might sound a bit funny, since |
| - lrz-test happens before z-test. But as long as a couple |
| - conditions are maintained this allows using lrz-test in |
| - cases where fragment shader has kill/discard: |
| - |
| - 1) Disable lrz-write in cases where it is uncertain during |
| - binning pass that a fragment will pass. Ie. if frag |
| - shader has-kill, writes-z, or alpha/stencil test is |
| - enabled. (For correctness, lrz-write must be disabled |
| - when blend is enabled.) This is analogous to how a |
| - z-prepass works. |
| - |
| - 2) Disable lrz-write and test if a depth-test direction |
| - reversal is detected. Due to condition (1), the contents |
| - of the lrz buffer are a conservative estimation of the |
| - depth buffer during the draw pass. Meaning that geometry |
| - that we know for certain will not be visible will not pass |
| - lrz-test. But geometry which may be (or contributes to |
| - blend) will pass the lrz-test. |
| - |
| - This allows us to keep early-lrz-test in cases where the frag |
| - shader does not write-z (ie. we know the z-value before FS) |
| - and does not have side-effects (image/ssbo writes, etc), but |
| - does have kill/discard. Which turns out to be a common |
| - enough case that it is useful to keep early-lrz test against |
| - the conservative lrz buffer to discard fragments that we |
| - know will definitely not be visible. |
| - </doc> |
| - <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/> |
| - <doc>Not a real hw value, used internally by mesa</doc> |
| - <value value="0x3" name="A6XX_INVALID_ZTEST"/> |
| -</enum> |
| - |
| -<enum name="a6xx_tess_spacing"> |
| - <value value="0x0" name="TESS_EQUAL"/> |
| - <value value="0x2" name="TESS_FRACTIONAL_ODD"/> |
| - <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> |
| -</enum> |
| -<enum name="a6xx_tess_output"> |
| - <value value="0x0" name="TESS_POINTS"/> |
| - <value value="0x1" name="TESS_LINES"/> |
| - <value value="0x2" name="TESS_CW_TRIS"/> |
| - <value value="0x3" name="TESS_CCW_TRIS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_cp_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_CP_ALWAYS_COUNT"/> |
| - <value value="1" name="A7XX_PERF_CP_BUSY_GFX_CORE_IDLE"/> |
| - <value value="2" name="A7XX_PERF_CP_BUSY_CYCLES"/> |
| - <value value="3" name="A7XX_PERF_CP_NUM_PREEMPTIONS"/> |
| - <value value="4" name="A7XX_PERF_CP_PREEMPTION_REACTION_DELAY"/> |
| - <value value="5" name="A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> |
| - <value value="6" name="A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> |
| - <value value="7" name="A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> |
| - <value value="8" name="A7XX_PERF_CP_PREDICATED_DRAWS_KILLED"/> |
| - <value value="9" name="A7XX_PERF_CP_MODE_SWITCH"/> |
| - <value value="10" name="A7XX_PERF_CP_ZPASS_DONE"/> |
| - <value value="11" name="A7XX_PERF_CP_CONTEXT_DONE"/> |
| - <value value="12" name="A7XX_PERF_CP_CACHE_FLUSH"/> |
| - <value value="13" name="A7XX_PERF_CP_LONG_PREEMPTIONS"/> |
| - <value value="14" name="A7XX_PERF_CP_SQE_I_CACHE_STARVE"/> |
| - <value value="15" name="A7XX_PERF_CP_SQE_IDLE"/> |
| - <value value="16" name="A7XX_PERF_CP_SQE_PM4_STARVE_RB_IB"/> |
| - <value value="17" name="A7XX_PERF_CP_SQE_PM4_STARVE_SDS"/> |
| - <value value="18" name="A7XX_PERF_CP_SQE_MRB_STARVE"/> |
| - <value value="19" name="A7XX_PERF_CP_SQE_RRB_STARVE"/> |
| - <value value="20" name="A7XX_PERF_CP_SQE_VSD_STARVE"/> |
| - <value value="21" name="A7XX_PERF_CP_VSD_DECODE_STARVE"/> |
| - <value value="22" name="A7XX_PERF_CP_SQE_PIPE_OUT_STALL"/> |
| - <value value="23" name="A7XX_PERF_CP_SQE_SYNC_STALL"/> |
| - <value value="24" name="A7XX_PERF_CP_SQE_PM4_WFI_STALL"/> |
| - <value value="25" name="A7XX_PERF_CP_SQE_SYS_WFI_STALL"/> |
| - <value value="26" name="A7XX_PERF_CP_SQE_T4_EXEC"/> |
| - <value value="27" name="A7XX_PERF_CP_SQE_LOAD_STATE_EXEC"/> |
| - <value value="28" name="A7XX_PERF_CP_SQE_SAVE_SDS_STATE"/> |
| - <value value="29" name="A7XX_PERF_CP_SQE_DRAW_EXEC"/> |
| - <value value="30" name="A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> |
| - <value value="31" name="A7XX_PERF_CP_SQE_EXEC_PROFILED"/> |
| - <value value="32" name="A7XX_PERF_CP_MEMORY_POOL_EMPTY"/> |
| - <value value="33" name="A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL"/> |
| - <value value="34" name="A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> |
| - <value value="35" name="A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> |
| - <value value="36" name="A7XX_PERF_CP_AHB_STALL_SQE_GMU"/> |
| - <value value="37" name="A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER"/> |
| - <value value="38" name="A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER"/> |
| - <value value="39" name="A7XX_PERF_CP_CLUSTER0_EMPTY"/> |
| - <value value="40" name="A7XX_PERF_CP_CLUSTER1_EMPTY"/> |
| - <value value="41" name="A7XX_PERF_CP_CLUSTER2_EMPTY"/> |
| - <value value="42" name="A7XX_PERF_CP_CLUSTER3_EMPTY"/> |
| - <value value="43" name="A7XX_PERF_CP_CLUSTER4_EMPTY"/> |
| - <value value="44" name="A7XX_PERF_CP_CLUSTER5_EMPTY"/> |
| - <value value="45" name="A7XX_PERF_CP_PM4_DATA"/> |
| - <value value="46" name="A7XX_PERF_CP_PM4_HEADERS"/> |
| - <value value="47" name="A7XX_PERF_CP_VBIF_READ_BEATS"/> |
| - <value value="48" name="A7XX_PERF_CP_VBIF_WRITE_BEATS"/> |
| - <value value="49" name="A7XX_PERF_CP_SQE_INSTR_COUNTER"/> |
| - <value value="50" name="A7XX_PERF_CP_RESERVED_50"/> |
| - <value value="51" name="A7XX_PERF_CP_RESERVED_51"/> |
| - <value value="52" name="A7XX_PERF_CP_RESERVED_52"/> |
| - <value value="53" name="A7XX_PERF_CP_RESERVED_53"/> |
| - <value value="54" name="A7XX_PERF_CP_RESERVED_54"/> |
| - <value value="55" name="A7XX_PERF_CP_RESERVED_55"/> |
| - <value value="56" name="A7XX_PERF_CP_RESERVED_56"/> |
| - <value value="57" name="A7XX_PERF_CP_RESERVED_57"/> |
| - <value value="58" name="A7XX_PERF_CP_RESERVED_58"/> |
| - <value value="59" name="A7XX_PERF_CP_RESERVED_59"/> |
| - <value value="60" name="A7XX_PERF_CP_CLUSTER0_FULL"/> |
| - <value value="61" name="A7XX_PERF_CP_CLUSTER1_FULL"/> |
| - <value value="62" name="A7XX_PERF_CP_CLUSTER2_FULL"/> |
| - <value value="63" name="A7XX_PERF_CP_CLUSTER3_FULL"/> |
| - <value value="64" name="A7XX_PERF_CP_CLUSTER4_FULL"/> |
| - <value value="65" name="A7XX_PERF_CP_CLUSTER5_FULL"/> |
| - <value value="66" name="A7XX_PERF_CP_CLUSTER6_FULL"/> |
| - <value value="67" name="A7XX_PERF_CP_CLUSTER6_EMPTY"/> |
| - <value value="68" name="A7XX_PERF_CP_ICACHE_MISSES"/> |
| - <value value="69" name="A7XX_PERF_CP_ICACHE_HITS"/> |
| - <value value="70" name="A7XX_PERF_CP_ICACHE_STALL"/> |
| - <value value="71" name="A7XX_PERF_CP_DCACHE_MISSES"/> |
| - <value value="72" name="A7XX_PERF_CP_DCACHE_HITS"/> |
| - <value value="73" name="A7XX_PERF_CP_DCACHE_STALLS"/> |
| - <value value="74" name="A7XX_PERF_CP_AQE_SQE_STALL"/> |
| - <value value="75" name="A7XX_PERF_CP_SQE_AQE_STARVE"/> |
| - <value value="76" name="A7XX_PERF_CP_PREEMPT_LATENCY"/> |
| - <value value="77" name="A7XX_PERF_CP_SQE_MD8_STALL_CYCLES"/> |
| - <value value="78" name="A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES"/> |
| - <value value="79" name="A7XX_PERF_CP_AQE_NUM_AS_CHUNKS"/> |
| - <value value="80" name="A7XX_PERF_CP_AQE_NUM_MS_CHUNKS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_rbbm_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_RBBM_ALWAYS_COUNT"/> |
| - <value value="1" name="A7XX_PERF_RBBM_ALWAYS_ON"/> |
| - <value value="2" name="A7XX_PERF_RBBM_TSE_BUSY"/> |
| - <value value="3" name="A7XX_PERF_RBBM_RAS_BUSY"/> |
| - <value value="4" name="A7XX_PERF_RBBM_PC_DCALL_BUSY"/> |
| - <value value="5" name="A7XX_PERF_RBBM_PC_VSD_BUSY"/> |
| - <value value="6" name="A7XX_PERF_RBBM_STATUS_MASKED"/> |
| - <value value="7" name="A7XX_PERF_RBBM_COM_BUSY"/> |
| - <value value="8" name="A7XX_PERF_RBBM_DCOM_BUSY"/> |
| - <value value="9" name="A7XX_PERF_RBBM_VBIF_BUSY"/> |
| - <value value="10" name="A7XX_PERF_RBBM_VSC_BUSY"/> |
| - <value value="11" name="A7XX_PERF_RBBM_TESS_BUSY"/> |
| - <value value="12" name="A7XX_PERF_RBBM_UCHE_BUSY"/> |
| - <value value="13" name="A7XX_PERF_RBBM_HLSQ_BUSY"/> |
| -</enum> |
| - |
| -<enum name="a7xx_pc_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_PC_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_PC_WORKING_CYCLES"/> |
| - <value value="2" name="A7XX_PERF_PC_STALL_CYCLES_VFD"/> |
| - <value value="3" name="A7XX_PERF_PC_RESERVED"/> |
| - <value value="4" name="A7XX_PERF_PC_STALL_CYCLES_VPC"/> |
| - <value value="5" name="A7XX_PERF_PC_STALL_CYCLES_UCHE"/> |
| - <value value="6" name="A7XX_PERF_PC_STALL_CYCLES_TESS"/> |
| - <value value="7" name="A7XX_PERF_PC_STALL_CYCLES_VFD_ONLY"/> |
| - <value value="8" name="A7XX_PERF_PC_STALL_CYCLES_VPC_ONLY"/> |
| - <value value="9" name="A7XX_PERF_PC_PASS1_TF_STALL_CYCLES"/> |
| - <value value="10" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_INDEX"/> |
| - <value value="11" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> |
| - <value value="12" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> |
| - <value value="13" name="A7XX_PERF_PC_STARVE_CYCLES_DI"/> |
| - <value value="14" name="A7XX_PERF_PC_VIS_STREAMS_LOADED"/> |
| - <value value="15" name="A7XX_PERF_PC_INSTANCES"/> |
| - <value value="16" name="A7XX_PERF_PC_VPC_PRIMITIVES"/> |
| - <value value="17" name="A7XX_PERF_PC_DEAD_PRIM"/> |
| - <value value="18" name="A7XX_PERF_PC_LIVE_PRIM"/> |
| - <value value="19" name="A7XX_PERF_PC_VERTEX_HITS"/> |
| - <value value="20" name="A7XX_PERF_PC_IA_VERTICES"/> |
| - <value value="21" name="A7XX_PERF_PC_IA_PRIMITIVES"/> |
| - <value value="22" name="A7XX_PERF_PC_RESERVED_22"/> |
| - <value value="23" name="A7XX_PERF_PC_HS_INVOCATIONS"/> |
| - <value value="24" name="A7XX_PERF_PC_DS_INVOCATIONS"/> |
| - <value value="25" name="A7XX_PERF_PC_VS_INVOCATIONS"/> |
| - <value value="26" name="A7XX_PERF_PC_GS_INVOCATIONS"/> |
| - <value value="27" name="A7XX_PERF_PC_DS_PRIMITIVES"/> |
| - <value value="28" name="A7XX_PERF_PC_3D_DRAWCALLS"/> |
| - <value value="29" name="A7XX_PERF_PC_2D_DRAWCALLS"/> |
| - <value value="30" name="A7XX_PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> |
| - <value value="31" name="A7XX_PERF_PC_TESS_BUSY_CYCLES"/> |
| - <value value="32" name="A7XX_PERF_PC_TESS_WORKING_CYCLES"/> |
| - <value value="33" name="A7XX_PERF_PC_TESS_STALL_CYCLES_PC"/> |
| - <value value="34" name="A7XX_PERF_PC_TESS_STARVE_CYCLES_PC"/> |
| - <value value="35" name="A7XX_PERF_PC_TESS_SINGLE_PRIM_CYCLES"/> |
| - <value value="36" name="A7XX_PERF_PC_TESS_PC_UV_TRANS"/> |
| - <value value="37" name="A7XX_PERF_PC_TESS_PC_UV_PATCHES"/> |
| - <value value="38" name="A7XX_PERF_PC_TESS_FACTOR_TRANS"/> |
| - <value value="39" name="A7XX_PERF_PC_TAG_CHECKED_VERTICES"/> |
| - <value value="40" name="A7XX_PERF_PC_MESH_VS_WAVES"/> |
| - <value value="41" name="A7XX_PERF_PC_MESH_DRAWS"/> |
| - <value value="42" name="A7XX_PERF_PC_MESH_DEAD_DRAWS"/> |
| - <value value="43" name="A7XX_PERF_PC_MESH_MVIS_EN_DRAWS"/> |
| - <value value="44" name="A7XX_PERF_PC_MESH_DEAD_PRIM"/> |
| - <value value="45" name="A7XX_PERF_PC_MESH_LIVE_PRIM"/> |
| - <value value="46" name="A7XX_PERF_PC_MESH_PA_EN_PRIM"/> |
| - <value value="47" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_MVIS_STREAM"/> |
| - <value value="48" name="A7XX_PERF_PC_STARVE_CYCLES_PREDRAW"/> |
| - <value value="49" name="A7XX_PERF_PC_STALL_CYCLES_COMPUTE_GFX"/> |
| - <value value="50" name="A7XX_PERF_PC_STALL_CYCLES_GFX_COMPUTE"/> |
| - <value value="51" name="A7XX_PERF_PC_TESS_PC_MULTI_PATCH_TRANS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_vfd_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_VFD_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_VFD_STALL_CYCLES_UCHE"/> |
| - <value value="2" name="A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> |
| - <value value="3" name="A7XX_PERF_VFD_STALL_CYCLES_SP_INFO"/> |
| - <value value="4" name="A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR"/> |
| - <value value="5" name="A7XX_PERF_VFD_STARVE_CYCLES_UCHE"/> |
| - <value value="6" name="A7XX_PERF_VFD_RBUFFER_FULL"/> |
| - <value value="7" name="A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL"/> |
| - <value value="8" name="A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> |
| - <value value="9" name="A7XX_PERF_VFD_NUM_ATTRIBUTES"/> |
| - <value value="10" name="A7XX_PERF_VFD_UPPER_SHADER_FIBERS"/> |
| - <value value="11" name="A7XX_PERF_VFD_LOWER_SHADER_FIBERS"/> |
| - <value value="12" name="A7XX_PERF_VFD_MODE_0_FIBERS"/> |
| - <value value="13" name="A7XX_PERF_VFD_MODE_1_FIBERS"/> |
| - <value value="14" name="A7XX_PERF_VFD_MODE_2_FIBERS"/> |
| - <value value="15" name="A7XX_PERF_VFD_MODE_3_FIBERS"/> |
| - <value value="16" name="A7XX_PERF_VFD_MODE_4_FIBERS"/> |
| - <value value="17" name="A7XX_PERF_VFD_TOTAL_VERTICES"/> |
| - <value value="18" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD"/> |
| - <value value="19" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> |
| - <value value="20" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG"/> |
| - <value value="21" name="A7XX_PERF_VFDP_STARVE_CYCLES_PC"/> |
| - <value value="22" name="A7XX_PERF_VFDP_VS_STAGE_WAVES"/> |
| - <value value="23" name="A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE"/> |
| - <value value="24" name="A7XX_PERF_VFD_STALL_CYCLES_CBSYNC"/> |
| -</enum> |
| - |
| -<enum name="a7xx_hlsq_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_HLSQ_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_HLSQ_STALL_CYCLES_UCHE"/> |
| - <value value="2" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE"/> |
| - <value value="3" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> |
| - <value value="4" name="A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES"/> |
| - <value value="5" name="A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT"/> |
| - <value value="6" name="A7XX_PERF_HLSQ_RESERVED_6"/> |
| - <value value="7" name="A7XX_PERF_HLSQ_RESERVED_7"/> |
| - <value value="8" name="A7XX_PERF_HLSQ_RESERVED_8"/> |
| - <value value="9" name="A7XX_PERF_HLSQ_RESERVED_9"/> |
| - <value value="10" name="A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS"/> |
| - <value value="11" name="A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> |
| - <value value="12" name="A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> |
| - <value value="13" name="A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> |
| - <value value="14" name="A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> |
| - <value value="15" name="A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> |
| - <value value="16" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> |
| - <value value="17" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> |
| - <value value="18" name="A7XX_PERF_HLSQ_STALL_CYCLES_VPC"/> |
| - <value value="19" name="A7XX_PERF_HLSQ_RESERVED_19"/> |
| - <value value="20" name="A7XX_PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> |
| - <value value="21" name="A7XX_PERF_HLSQ_VSBR_STALL_CYCLES"/> |
| - <value value="22" name="A7XX_PERF_HLSQ_FS_STALL_CYCLES"/> |
| - <value value="23" name="A7XX_PERF_HLSQ_LPAC_STALL_CYCLES"/> |
| - <value value="24" name="A7XX_PERF_HLSQ_BV_STALL_CYCLES"/> |
| - <value value="25" name="A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES"/> |
| - <value value="26" name="A7XX_PERF_HLSQ_FS_DEREF_CYCLES"/> |
| - <value value="27" name="A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES"/> |
| - <value value="28" name="A7XX_PERF_HLSQ_BV_DEREF_CYCLES"/> |
| - <value value="29" name="A7XX_PERF_HLSQ_VSBR_S2W_CYCLES"/> |
| - <value value="30" name="A7XX_PERF_HLSQ_FS_S2W_CYCLES"/> |
| - <value value="31" name="A7XX_PERF_HLSQ_LPAC_S2W_CYCLES"/> |
| - <value value="32" name="A7XX_PERF_HLSQ_BV_S2W_CYCLES"/> |
| - <value value="33" name="A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W"/> |
| - <value value="34" name="A7XX_PERF_HLSQ_FS_WAIT_VS_S2W"/> |
| - <value value="35" name="A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W"/> |
| - <value value="36" name="A7XX_PERF_HLSQ_BV_WAIT_FS_S2W"/> |
| - <value value="37" name="A7XX_PERF_HLSQ_VS_WAIT_CONST_RESOURCE"/> |
| - <value value="38" name="A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W"/> |
| - <value value="39" name="A7XX_PERF_HLSQ_FS_STARVING_SP"/> |
| - <value value="40" name="A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING"/> |
| - <value value="41" name="A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING"/> |
| - <value value="42" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS"/> |
| - <value value="43" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS"/> |
| - <value value="44" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS"/> |
| - <value value="45" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS"/> |
| - <value value="46" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV"/> |
| - <value value="47" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV"/> |
| - <value value="48" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC"/> |
| - <value value="49" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC"/> |
| - <value value="50" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS"/> |
| - <value value="51" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS"/> |
| - <value value="52" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV"/> |
| - <value value="53" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC"/> |
| - <value value="54" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS"/> |
| - <value value="55" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS"/> |
| - <value value="56" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV"/> |
| - <value value="57" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC"/> |
| -</enum> |
| - |
| -<enum name="a7xx_vpc_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_VPC_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_VPC_WORKING_CYCLES"/> |
| - <value value="2" name="A7XX_PERF_VPC_STALL_CYCLES_UCHE"/> |
| - <value value="3" name="A7XX_PERF_VPC_STALL_CYCLES_VFD_WACK"/> |
| - <value value="4" name="A7XX_PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> |
| - <value value="5" name="A7XX_PERF_VPC_RESERVED_5"/> |
| - <value value="6" name="A7XX_PERF_VPC_STALL_CYCLES_SP_LM"/> |
| - <value value="7" name="A7XX_PERF_VPC_STARVE_CYCLES_SP"/> |
| - <value value="8" name="A7XX_PERF_VPC_STARVE_CYCLES_LRZ"/> |
| - <value value="9" name="A7XX_PERF_VPC_PC_PRIMITIVES"/> |
| - <value value="10" name="A7XX_PERF_VPC_SP_COMPONENTS"/> |
| - <value value="11" name="A7XX_PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> |
| - <value value="12" name="A7XX_PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> |
| - <value value="13" name="A7XX_PERF_VPC_RB_VISIBLE_PRIMITIVES"/> |
| - <value value="14" name="A7XX_PERF_VPC_LM_TRANSACTION"/> |
| - <value value="15" name="A7XX_PERF_VPC_STREAMOUT_TRANSACTION"/> |
| - <value value="16" name="A7XX_PERF_VPC_VS_BUSY_CYCLES"/> |
| - <value value="17" name="A7XX_PERF_VPC_PS_BUSY_CYCLES"/> |
| - <value value="18" name="A7XX_PERF_VPC_VS_WORKING_CYCLES"/> |
| - <value value="19" name="A7XX_PERF_VPC_PS_WORKING_CYCLES"/> |
| - <value value="20" name="A7XX_PERF_VPC_STARVE_CYCLES_RB"/> |
| - <value value="21" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_POS"/> |
| - <value value="22" name="A7XX_PERF_VPC_WIT_FULL_CYCLES"/> |
| - <value value="23" name="A7XX_PERF_VPC_VPCRAM_FULL_CYCLES"/> |
| - <value value="24" name="A7XX_PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> |
| - <value value="25" name="A7XX_PERF_VPC_NUM_VPCRAM_WRITE"/> |
| - <value value="26" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_SO"/> |
| - <value value="27" name="A7XX_PERF_VPC_NUM_ATTR_REQ_LM"/> |
| - <value value="28" name="A7XX_PERF_VPC_STALL_CYCLE_TSE"/> |
| - <value value="29" name="A7XX_PERF_VPC_TSE_PRIMITIVES"/> |
| - <value value="30" name="A7XX_PERF_VPC_GS_PRIMITIVES"/> |
| - <value value="31" name="A7XX_PERF_VPC_TSE_TRANSACTIONS"/> |
| - <value value="32" name="A7XX_PERF_VPC_STALL_CYCLES_CCU"/> |
| - <value value="33" name="A7XX_PERF_VPC_NUM_WM_HIT"/> |
| - <value value="34" name="A7XX_PERF_VPC_STALL_DQ_WACK"/> |
| - <value value="35" name="A7XX_PERF_VPC_STALL_CYCLES_CCHE"/> |
| - <value value="36" name="A7XX_PERF_VPC_STARVE_CYCLES_CCHE"/> |
| - <value value="37" name="A7XX_PERF_VPC_NUM_PA_REQ"/> |
| - <value value="38" name="A7XX_PERF_VPC_NUM_LM_REQ_HIT"/> |
| - <value value="39" name="A7XX_PERF_VPC_CCHE_REQBUF_FULL"/> |
| - <value value="40" name="A7XX_PERF_VPC_STALL_CYCLES_LM_ACK"/> |
| - <value value="41" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_FE"/> |
| - <value value="42" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_PCVS"/> |
| - <value value="43" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_VPCPS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_tse_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_TSE_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_TSE_CLIPPING_CYCLES"/> |
| - <value value="2" name="A7XX_PERF_TSE_STALL_CYCLES_RAS"/> |
| - <value value="3" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> |
| - <value value="4" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> |
| - <value value="5" name="A7XX_PERF_TSE_STARVE_CYCLES_PC"/> |
| - <value value="6" name="A7XX_PERF_TSE_INPUT_PRIM"/> |
| - <value value="7" name="A7XX_PERF_TSE_INPUT_NULL_PRIM"/> |
| - <value value="8" name="A7XX_PERF_TSE_TRIVAL_REJ_PRIM"/> |
| - <value value="9" name="A7XX_PERF_TSE_CLIPPED_PRIM"/> |
| - <value value="10" name="A7XX_PERF_TSE_ZERO_AREA_PRIM"/> |
| - <value value="11" name="A7XX_PERF_TSE_FACENESS_CULLED_PRIM"/> |
| - <value value="12" name="A7XX_PERF_TSE_ZERO_PIXEL_PRIM"/> |
| - <value value="13" name="A7XX_PERF_TSE_OUTPUT_NULL_PRIM"/> |
| - <value value="14" name="A7XX_PERF_TSE_OUTPUT_VISIBLE_PRIM"/> |
| - <value value="15" name="A7XX_PERF_TSE_CINVOCATION"/> |
| - <value value="16" name="A7XX_PERF_TSE_CPRIMITIVES"/> |
| - <value value="17" name="A7XX_PERF_TSE_2D_INPUT_PRIM"/> |
| - <value value="18" name="A7XX_PERF_TSE_2D_ALIVE_CYCLES"/> |
| - <value value="19" name="A7XX_PERF_TSE_CLIP_PLANES"/> |
| -</enum> |
| - |
| -<enum name="a7xx_ras_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_RAS_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> |
| - <value value="2" name="A7XX_PERF_RAS_STALL_CYCLES_LRZ"/> |
| - <value value="3" name="A7XX_PERF_RAS_STARVE_CYCLES_TSE"/> |
| - <value value="4" name="A7XX_PERF_RAS_SUPER_TILES"/> |
| - <value value="5" name="A7XX_PERF_RAS_8X4_TILES"/> |
| - <value value="6" name="A7XX_PERF_RAS_MASKGEN_ACTIVE"/> |
| - <value value="7" name="A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES"/> |
| - <value value="8" name="A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES"/> |
| - <value value="9" name="A7XX_PERF_RAS_PRIM_KILLED_INVISILBE"/> |
| - <value value="10" name="A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> |
| - <value value="11" name="A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> |
| - <value value="12" name="A7XX_PERF_RAS_BLOCKS"/> |
| - <value value="13" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_l2"/> |
| - <value value="14" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_l2"/> |
| - <value value="15" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_l2"/> |
| - <value value="16" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_l2"/> |
| - <value value="17" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_l2"/> |
| - <value value="18" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_l2"/> |
| - <value value="19" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_l2"/> |
| - <value value="20" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_l2"/> |
| - <value value="21" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_l2"/> |
| - <value value="22" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_l2"/> |
| - <value value="23" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_l2"/> |
| - <value value="24" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_l2"/> |
| - <value value="25" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_l2"/> |
| - <value value="26" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_l2"/> |
| - <value value="27" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_l2"/> |
| - <value value="28" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_l2"/> |
| - <value value="29" name="A7XX_PERF_RAS_FALSE_PARTIAL_STILE"/> |
| - |
| -</enum> |
| - |
| -<enum name="a7xx_uche_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_UCHE_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_UCHE_STALL_CYCLES_ARBITER"/> |
| - <value value="2" name="A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES"/> |
| - <value value="3" name="A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES"/> |
| - <value value="4" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_TP"/> |
| - <value value="5" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD"/> |
| - <value value="6" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> |
| - <value value="7" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ"/> |
| - <value value="8" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_SP"/> |
| - <value value="9" name="A7XX_PERF_UCHE_READ_REQUESTS_TP"/> |
| - <value value="10" name="A7XX_PERF_UCHE_READ_REQUESTS_VFD"/> |
| - <value value="11" name="A7XX_PERF_UCHE_READ_REQUESTS_HLSQ"/> |
| - <value value="12" name="A7XX_PERF_UCHE_READ_REQUESTS_LRZ"/> |
| - <value value="13" name="A7XX_PERF_UCHE_READ_REQUESTS_SP"/> |
| - <value value="14" name="A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ"/> |
| - <value value="15" name="A7XX_PERF_UCHE_WRITE_REQUESTS_SP"/> |
| - <value value="16" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VPC"/> |
| - <value value="17" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VSC"/> |
| - <value value="18" name="A7XX_PERF_UCHE_EVICTS"/> |
| - <value value="19" name="A7XX_PERF_UCHE_BANK_REQ0"/> |
| - <value value="20" name="A7XX_PERF_UCHE_BANK_REQ1"/> |
| - <value value="21" name="A7XX_PERF_UCHE_BANK_REQ2"/> |
| - <value value="22" name="A7XX_PERF_UCHE_BANK_REQ3"/> |
| - <value value="23" name="A7XX_PERF_UCHE_BANK_REQ4"/> |
| - <value value="24" name="A7XX_PERF_UCHE_BANK_REQ5"/> |
| - <value value="25" name="A7XX_PERF_UCHE_BANK_REQ6"/> |
| - <value value="26" name="A7XX_PERF_UCHE_BANK_REQ7"/> |
| - <value value="27" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0"/> |
| - <value value="28" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1"/> |
| - <value value="29" name="A7XX_PERF_UCHE_GMEM_READ_BEATS"/> |
| - <value value="30" name="A7XX_PERF_UCHE_TPH_REF_FULL"/> |
| - <value value="31" name="A7XX_PERF_UCHE_TPH_VICTIM_FULL"/> |
| - <value value="32" name="A7XX_PERF_UCHE_TPH_EXT_FULL"/> |
| - <value value="33" name="A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA"/> |
| - <value value="34" name="A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES"/> |
| - <value value="35" name="A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES"/> |
| - <value value="36" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_PC"/> |
| - <value value="37" name="A7XX_PERF_UCHE_READ_REQUESTS_PC"/> |
| - <value value="38" name="A7XX_PERF_UCHE_RAM_READ_REQ"/> |
| - <value value="39" name="A7XX_PERF_UCHE_RAM_WRITE_REQ"/> |
| - <value value="40" name="A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP"/> |
| - <value value="41" name="A7XX_PERF_UCHE_STALL_CYCLES_DECMP"/> |
| - <value value="42" name="A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF"/> |
| - <value value="43" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC"/> |
| - <value value="44" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_NONUBWC"/> |
| - <value value="45" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM"/> |
| - <value value="46" name="A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS_KAILUA"/> |
| - <value value="47" name="A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS_KAILUA"/> |
| - <value value="48" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE"/> |
| - <value value="49" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER_KAILUA"/> |
| - <value value="50" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE"/> |
| - <value value="51" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS"/> |
| - <value value="52" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0"/> |
| - <value value="53" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1"/> |
| - <value value="54" name="A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL"/> |
| - <value value="55" name="A7XX_PERF_UCHE_CCHE_DPH_QUEUE_FULL"/> |
| - <value value="56" name="A7XX_PERF_UCHE_GMEM_WRITE_BEATS"/> |
| - <value value="57" name="A7XX_PERF_UCHE_UBWC_READ_BEATS"/> |
| - <value value="58" name="A7XX_PERF_UCHE_UBWC_WRITE_BEATS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_tp_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_TP_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_TP_STALL_CYCLES_UCHE"/> |
| - <value value="2" name="A7XX_PERF_TP_LATENCY_CYCLES"/> |
| - <value value="3" name="A7XX_PERF_TP_LATENCY_TRANS"/> |
| - <value value="4" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES"/> |
| - <value value="5" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES"/> |
| - <value value="6" name="A7XX_PERF_TP_L1_CACHELINE_REQUESTS"/> |
| - <value value="7" name="A7XX_PERF_TP_L1_CACHELINE_MISSES"/> |
| - <value value="8" name="A7XX_PERF_TP_SP_TP_TRANS"/> |
| - <value value="9" name="A7XX_PERF_TP_TP_SP_TRANS"/> |
| - <value value="10" name="A7XX_PERF_TP_OUTPUT_PIXELS"/> |
| - <value value="11" name="A7XX_PERF_TP_FILTER_WORKLOAD_16BIT"/> |
| - <value value="12" name="A7XX_PERF_TP_FILTER_WORKLOAD_32BIT"/> |
| - <value value="13" name="A7XX_PERF_TP_QUADS_RECEIVED"/> |
| - <value value="14" name="A7XX_PERF_TP_QUADS_OFFSET"/> |
| - <value value="15" name="A7XX_PERF_TP_QUADS_SHADOW"/> |
| - <value value="16" name="A7XX_PERF_TP_QUADS_ARRAY"/> |
| - <value value="17" name="A7XX_PERF_TP_QUADS_GRADIENT"/> |
| - <value value="18" name="A7XX_PERF_TP_QUADS_1D"/> |
| - <value value="19" name="A7XX_PERF_TP_QUADS_2D"/> |
| - <value value="20" name="A7XX_PERF_TP_QUADS_BUFFER"/> |
| - <value value="21" name="A7XX_PERF_TP_QUADS_3D"/> |
| - <value value="22" name="A7XX_PERF_TP_QUADS_CUBE"/> |
| - <value value="23" name="A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED"/> |
| - <value value="24" name="A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS"/> |
| - <value value="25" name="A7XX_PERF_TP_OUTPUT_PIXELS_POINT"/> |
| - <value value="26" name="A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR"/> |
| - <value value="27" name="A7XX_PERF_TP_OUTPUT_PIXELS_MIP"/> |
| - <value value="28" name="A7XX_PERF_TP_OUTPUT_PIXELS_ANISO"/> |
| - <value value="29" name="A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> |
| - <value value="30" name="A7XX_PERF_TP_FLAG_CACHE_REQUESTS"/> |
| - <value value="31" name="A7XX_PERF_TP_FLAG_CACHE_MISSES"/> |
| - <value value="32" name="A7XX_PERF_TP_L1_5_L2_REQUESTS"/> |
| - <value value="33" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS"/> |
| - <value value="34" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT"/> |
| - <value value="35" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> |
| - <value value="36" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> |
| - <value value="37" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> |
| - <value value="38" name="A7XX_PERF_TP_TPA2TPC_TRANS"/> |
| - <value value="39" name="A7XX_PERF_TP_L1_MISSES_ASTC_1TILE"/> |
| - <value value="40" name="A7XX_PERF_TP_L1_MISSES_ASTC_2TILE"/> |
| - <value value="41" name="A7XX_PERF_TP_L1_MISSES_ASTC_4TILE"/> |
| - <value value="42" name="A7XX_PERF_TP_L1_5_COMPRESS_REQS"/> |
| - <value value="43" name="A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS"/> |
| - <value value="44" name="A7XX_PERF_TP_L1_BANK_CONFLICT"/> |
| - <value value="45" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> |
| - <value value="46" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS"/> |
| - <value value="47" name="A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> |
| - <value value="48" name="A7XX_PERF_TP_FRONTEND_WORKING_CYCLES"/> |
| - <value value="49" name="A7XX_PERF_TP_L1_TAG_WORKING_CYCLES"/> |
| - <value value="50" name="A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> |
| - <value value="51" name="A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> |
| - <value value="52" name="A7XX_PERF_TP_BACKEND_WORKING_CYCLES"/> |
| - <value value="53" name="A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> |
| - <value value="54" name="A7XX_PERF_TP_STARVE_CYCLES_SP"/> |
| - <value value="55" name="A7XX_PERF_TP_STARVE_CYCLES_UCHE"/> |
| - <value value="56" name="A7XX_PERF_TP_STALL_CYCLES_UFC"/> |
| - <value value="57" name="A7XX_PERF_TP_FORMAT_DECOMP"/> |
| - <value value="58" name="A7XX_PERF_TP_FILTER_POINT_FP16"/> |
| - <value value="59" name="A7XX_PERF_TP_FILTER_POINT_FP32"/> |
| - <value value="60" name="A7XX_PERF_TP_LATENCY_FIFO_FULL"/> |
| - <value value="61" name="A7XX_PERF_TP_RESERVED_61"/> |
| - <value value="62" name="A7XX_PERF_TP_RESERVED_62"/> |
| - <value value="63" name="A7XX_PERF_TP_RESERVED_63"/> |
| - <value value="64" name="A7XX_PERF_TP_RESERVED_64"/> |
| - <value value="65" name="A7XX_PERF_TP_RESERVED_65"/> |
| - <value value="66" name="A7XX_PERF_TP_RESERVED_66"/> |
| - <value value="67" name="A7XX_PERF_TP_RESERVED_67"/> |
| - <value value="68" name="A7XX_PERF_TP_RESERVED_68"/> |
| - <value value="69" name="A7XX_PERF_TP_RESERVED_69"/> |
| - <value value="70" name="A7XX_PERF_TP_RESERVED_70"/> |
| - <value value="71" name="A7XX_PERF_TP_RESERVED_71"/> |
| - <value value="72" name="A7XX_PERF_TP_RESERVED_72"/> |
| - <value value="73" name="A7XX_PERF_TP_RESERVED_73"/> |
| - <value value="74" name="A7XX_PERF_TP_RESERVED_74"/> |
| - <value value="75" name="A7XX_PERF_TP_RESERVED_75"/> |
| - <value value="76" name="A7XX_PERF_TP_RESERVED_76"/> |
| - <value value="77" name="A7XX_PERF_TP_RESERVED_77"/> |
| - <value value="78" name="A7XX_PERF_TP_RESERVED_78"/> |
| - <value value="79" name="A7XX_PERF_TP_RESERVED_79"/> |
| - <value value="80" name="A7XX_PERF_TP_RESERVED_80"/> |
| - <value value="81" name="A7XX_PERF_TP_RESERVED_81"/> |
| - <value value="82" name="A7XX_PERF_TP_RESERVED_82"/> |
| - <value value="83" name="A7XX_PERF_TP_RESERVED_83"/> |
| - <value value="84" name="A7XX_PERF_TP_RESERVED_84"/> |
| - <value value="85" name="A7XX_PERF_TP_RESERVED_85"/> |
| - <value value="86" name="A7XX_PERF_TP_RESERVED_86"/> |
| - <value value="87" name="A7XX_PERF_TP_RESERVED_87"/> |
| - <value value="88" name="A7XX_PERF_TP_RESERVED_88"/> |
| - <value value="89" name="A7XX_PERF_TP_RESERVED_89"/> |
| - <value value="90" name="A7XX_PERF_TP_RESERVED_90"/> |
| - <value value="91" name="A7XX_PERF_TP_RESERVED_91"/> |
| - <value value="92" name="A7XX_PERF_TP_RESERVED_92"/> |
| - <value value="93" name="A7XX_PERF_TP_RESERVED_93"/> |
| - <value value="94" name="A7XX_PERF_TP_RESERVED_94"/> |
| - <value value="95" name="A7XX_PERF_TP_RESERVED_95"/> |
| - <value value="96" name="A7XX_PERF_TP_RESERVED_96"/> |
| - <value value="97" name="A7XX_PERF_TP_RESERVED_97"/> |
| - <value value="98" name="A7XX_PERF_TP_RESERVED_98"/> |
| - <value value="99" name="A7XX_PERF_TP_RESERVED_99"/> |
| - <value value="100" name="A7XX_PERF_TP_RESERVED_100"/> |
| - <value value="101" name="A7XX_PERF_TP_RESERVED_101"/> |
| - <value value="102" name="A7XX_PERF_TP_RESERVED_102"/> |
| - <value value="103" name="A7XX_PERF_TP_RESERVED_103"/> |
| - <value value="104" name="A7XX_PERF_TP_RESERVED_104"/> |
| - <value value="105" name="A7XX_PERF_TP_RESERVED_105"/> |
| - <value value="106" name="A7XX_PERF_TP_RESERVED_106"/> |
| - <value value="107" name="A7XX_PERF_TP_RESERVED_107"/> |
| - <value value="108" name="A7XX_PERF_TP_RESERVED_108"/> |
| - <value value="109" name="A7XX_PERF_TP_RESERVED_109"/> |
| - <value value="110" name="A7XX_PERF_TP_RESERVED_110"/> |
| - <value value="111" name="A7XX_PERF_TP_RESERVED_111"/> |
| - <value value="112" name="A7XX_PERF_TP_RESERVED_112"/> |
| - <value value="113" name="A7XX_PERF_TP_RESERVED_113"/> |
| - <value value="114" name="A7XX_PERF_TP_RESERVED_114"/> |
| - <value value="115" name="A7XX_PERF_TP_RESERVED_115"/> |
| - <value value="116" name="A7XX_PERF_TP_RESERVED_116"/> |
| - <value value="117" name="A7XX_PERF_TP_RESERVED_117"/> |
| - <value value="118" name="A7XX_PERF_TP_RESERVED_118"/> |
| - <value value="119" name="A7XX_PERF_TP_RESERVED_119"/> |
| - <value value="120" name="A7XX_PERF_TP_RESERVED_120"/> |
| - <value value="121" name="A7XX_PERF_TP_RESERVED_121"/> |
| - <value value="122" name="A7XX_PERF_TP_RESERVED_122"/> |
| - <value value="123" name="A7XX_PERF_TP_RESERVED_123"/> |
| - <value value="124" name="A7XX_PERF_TP_RESERVED_124"/> |
| - <value value="125" name="A7XX_PERF_TP_RESERVED_125"/> |
| - <value value="126" name="A7XX_PERF_TP_RESERVED_126"/> |
| - <value value="127" name="A7XX_PERF_TP_RESERVED_127"/> |
| - <value value="128" name="A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR"/> |
| - <value value="129" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16"/> |
| - <value value="130" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16"/> |
| - <value value="131" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32"/> |
| - <value value="132" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32"/> |
| -</enum> |
| - |
| -<enum name="a7xx_sp_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_SP_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_SP_ALU_WORKING_CYCLES"/> |
| - <value value="2" name="A7XX_PERF_SP_EFU_WORKING_CYCLES"/> |
| - <value value="3" name="A7XX_PERF_SP_STALL_CYCLES_VPC"/> |
| - <value value="4" name="A7XX_PERF_SP_STALL_CYCLES_TP"/> |
| - <value value="5" name="A7XX_PERF_SP_STALL_CYCLES_UCHE"/> |
| - <value value="6" name="A7XX_PERF_SP_STALL_CYCLES_RB"/> |
| - <value value="7" name="A7XX_PERF_SP_NON_EXECUTION_CYCLES"/> |
| - <value value="8" name="A7XX_PERF_SP_WAVE_CONTEXTS"/> |
| - <value value="9" name="A7XX_PERF_SP_WAVE_CONTEXT_CYCLES"/> |
| - <value value="10" name="A7XX_PERF_SP_STAGE_WAVE_CYCLES"/> |
| - <value value="11" name="A7XX_PERF_SP_STAGE_WAVE_SAMPLES"/> |
| - <value value="12" name="A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES"/> |
| - <value value="13" name="A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES"/> |
| - <value value="14" name="A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES"/> |
| - <value value="15" name="A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES"/> |
| - <value value="16" name="A7XX_PERF_SP_WAVE_CTRL_CYCLES"/> |
| - <value value="17" name="A7XX_PERF_SP_WAVE_LOAD_CYCLES"/> |
| - <value value="18" name="A7XX_PERF_SP_WAVE_EMIT_CYCLES"/> |
| - <value value="19" name="A7XX_PERF_SP_WAVE_NOP_CYCLES"/> |
| - <value value="20" name="A7XX_PERF_SP_WAVE_WAIT_CYCLES"/> |
| - <value value="21" name="A7XX_PERF_SP_WAVE_FETCH_CYCLES"/> |
| - <value value="22" name="A7XX_PERF_SP_WAVE_IDLE_CYCLES"/> |
| - <value value="23" name="A7XX_PERF_SP_WAVE_END_CYCLES"/> |
| - <value value="24" name="A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES"/> |
| - <value value="25" name="A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> |
| - <value value="26" name="A7XX_PERF_SP_WAVE_JOIN_CYCLES"/> |
| - <value value="27" name="A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS"/> |
| - <value value="28" name="A7XX_PERF_SP_LM_STORE_INSTRUCTIONS"/> |
| - <value value="29" name="A7XX_PERF_SP_LM_ATOMICS"/> |
| - <value value="30" name="A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS"/> |
| - <value value="31" name="A7XX_PERF_SP_GM_STORE_INSTRUCTIONS"/> |
| - <value value="32" name="A7XX_PERF_SP_GM_ATOMICS"/> |
| - <value value="33" name="A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> |
| - <value value="34" name="A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> |
| - <value value="35" name="A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| - <value value="36" name="A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| - <value value="37" name="A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> |
| - <value value="38" name="A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> |
| - <value value="39" name="A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> |
| - <value value="40" name="A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| - <value value="41" name="A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| - <value value="42" name="A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> |
| - <value value="43" name="A7XX_PERF_SP_VS_INSTRUCTIONS"/> |
| - <value value="44" name="A7XX_PERF_SP_FS_INSTRUCTIONS"/> |
| - <value value="45" name="A7XX_PERF_SP_ADDR_LOCK_COUNT"/> |
| - <value value="46" name="A7XX_PERF_SP_UCHE_READ_TRANS"/> |
| - <value value="47" name="A7XX_PERF_SP_UCHE_WRITE_TRANS"/> |
| - <value value="48" name="A7XX_PERF_SP_EXPORT_VPC_TRANS"/> |
| - <value value="49" name="A7XX_PERF_SP_EXPORT_RB_TRANS"/> |
| - <value value="50" name="A7XX_PERF_SP_PIXELS_KILLED"/> |
| - <value value="51" name="A7XX_PERF_SP_ICL1_REQUESTS"/> |
| - <value value="52" name="A7XX_PERF_SP_ICL1_MISSES"/> |
| - <value value="53" name="A7XX_PERF_SP_HS_INSTRUCTIONS"/> |
| - <value value="54" name="A7XX_PERF_SP_DS_INSTRUCTIONS"/> |
| - <value value="55" name="A7XX_PERF_SP_GS_INSTRUCTIONS"/> |
| - <value value="56" name="A7XX_PERF_SP_CS_INSTRUCTIONS"/> |
| - <value value="57" name="A7XX_PERF_SP_GPR_READ"/> |
| - <value value="58" name="A7XX_PERF_SP_GPR_WRITE"/> |
| - <value value="59" name="A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| - <value value="60" name="A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| - <value value="61" name="A7XX_PERF_SP_LM_BANK_CONFLICTS"/> |
| - <value value="62" name="A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> |
| - <value value="63" name="A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> |
| - <value value="64" name="A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> |
| - <value value="65" name="A7XX_PERF_SP_LM_WORKING_CYCLES"/> |
| - <value value="66" name="A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES"/> |
| - <value value="67" name="A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES"/> |
| - <value value="68" name="A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> |
| - <value value="69" name="A7XX_PERF_SP_STARVE_CYCLES_HLSQ"/> |
| - <value value="70" name="A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES"/> |
| - <value value="71" name="A7XX_PERF_SP_WORKING_EU"/> |
| - <value value="72" name="A7XX_PERF_SP_ANY_EU_WORKING"/> |
| - <value value="73" name="A7XX_PERF_SP_WORKING_EU_FS_STAGE"/> |
| - <value value="74" name="A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE"/> |
| - <value value="75" name="A7XX_PERF_SP_WORKING_EU_VS_STAGE"/> |
| - <value value="76" name="A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE"/> |
| - <value value="77" name="A7XX_PERF_SP_WORKING_EU_CS_STAGE"/> |
| - <value value="78" name="A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE"/> |
| - <value value="79" name="A7XX_PERF_SP_GPR_READ_PREFETCH"/> |
| - <value value="80" name="A7XX_PERF_SP_GPR_READ_CONFLICT"/> |
| - <value value="81" name="A7XX_PERF_SP_GPR_WRITE_CONFLICT"/> |
| - <value value="82" name="A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES"/> |
| - <value value="83" name="A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> |
| - <value value="84" name="A7XX_PERF_SP_EXECUTABLE_WAVES"/> |
| - <value value="85" name="A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES"/> |
| - <value value="86" name="A7XX_PERF_SP_WORKING_EU_LPAC"/> |
| - <value value="87" name="A7XX_PERF_SP_BYPASS_BUSY_CYCLES"/> |
| - <value value="88" name="A7XX_PERF_SP_ANY_EU_WORKING_LPAC"/> |
| - <value value="89" name="A7XX_PERF_SP_WAVE_ALU_CYCLES"/> |
| - <value value="90" name="A7XX_PERF_SP_WAVE_EFU_CYCLES"/> |
| - <value value="91" name="A7XX_PERF_SP_WAVE_INT_CYCLES"/> |
| - <value value="92" name="A7XX_PERF_SP_WAVE_CSP_CYCLES"/> |
| - <value value="93" name="A7XX_PERF_SP_EWAVE_CONTEXTS"/> |
| - <value value="94" name="A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES"/> |
| - <value value="95" name="A7XX_PERF_SP_LPAC_BUSY_CYCLES"/> |
| - <value value="96" name="A7XX_PERF_SP_LPAC_INSTRUCTIONS"/> |
| - <value value="97" name="A7XX_PERF_SP_FS_STAGE_1X_WAVES"/> |
| - <value value="98" name="A7XX_PERF_SP_FS_STAGE_2X_WAVES"/> |
| - <value value="99" name="A7XX_PERF_SP_QUADS"/> |
| - <value value="100" name="A7XX_PERF_SP_CS_INVOCATIONS"/> |
| - <value value="101" name="A7XX_PERF_SP_PIXELS"/> |
| - <value value="102" name="A7XX_PERF_SP_LPAC_DRAWCALLS"/> |
| - <value value="103" name="A7XX_PERF_SP_PI_WORKING_CYCLES"/> |
| - <value value="104" name="A7XX_PERF_SP_WAVE_INPUT_CYCLES"/> |
| - <value value="105" name="A7XX_PERF_SP_WAVE_OUTPUT_CYCLES"/> |
| - <value value="106" name="A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES"/> |
| - <value value="107" name="A7XX_PERF_SP_WAVE_HWAVE_SYNC"/> |
| - <value value="108" name="A7XX_PERF_SP_OUTPUT_3D_PIXELS"/> |
| - <value value="109" name="A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS"/> |
| - <value value="110" name="A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS"/> |
| - <value value="111" name="A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS"/> |
| - <value value="112" name="A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS"/> |
| - <value value="113" name="A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS"/> |
| - <value value="114" name="A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS"/> |
| - <value value="115" name="A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS"/> |
| - <value value="116" name="A7XX_PERF_SP_ALU_GPR_READ_CYCLES"/> |
| - <value value="117" name="A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES"/> |
| - <value value="118" name="A7XX_PERF_SP_LM_FULL_CYCLES"/> |
| - <value value="119" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES"/> |
| - <value value="120" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES"/> |
| - <value value="121" name="A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION"/> |
| - <value value="122" name="A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS"/> |
| - <value value="123" name="A7XX_PERF_SP_RBRT_KICKOFF_FIBERS"/> |
| - <value value="124" name="A7XX_PERF_SP_RBRT_KICKOFF_DQUADS"/> |
| - <value value="125" name="A7XX_PERF_SP_RTU_BUSY_CYCLES"/> |
| - <value value="126" name="A7XX_PERF_SP_RTU_L0_HITS"/> |
| - <value value="127" name="A7XX_PERF_SP_RTU_L0_MISSES"/> |
| - <value value="128" name="A7XX_PERF_SP_RTU_L0_HIT_ON_MISS"/> |
| - <value value="129" name="A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE"/> |
| - <value value="130" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE"/> |
| - <value value="131" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE"/> |
| - <value value="132" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE"/> |
| - <value value="133" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA"/> |
| - <value value="134" name="A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT"/> |
| - <value value="135" name="A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT"/> |
| - <value value="136" name="A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE"/> |
| - <value value="137" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0"/> |
| - <value value="138" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO"/> |
| - <value value="139" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES"/> |
| - <value value="140" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES"/> |
| - <value value="141" name="A7XX_PERF_SP_STCHE_MISS_INC_VS"/> |
| - <value value="142" name="A7XX_PERF_SP_STCHE_MISS_INC_FS"/> |
| - <value value="143" name="A7XX_PERF_SP_STCHE_MISS_INC_BV"/> |
| - <value value="144" name="A7XX_PERF_SP_STCHE_MISS_INC_LPAC"/> |
| - <value value="145" name="A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS"/> |
| - <value value="146" name="A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS"/> |
| - <value value="147" name="A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS"/> |
| - <value value="148" name="A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS"/> |
| - <value value="149" name="A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS"/> |
| - <value value="150" name="A7XX_PERF_SP_SCH_STALL_CYCLES_RTU"/> |
| -</enum> |
| - |
| -<enum name="a7xx_rb_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_RB_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_RB_STALL_CYCLES_HLSQ"/> |
| - <value value="2" name="A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL"/> |
| - <value value="3" name="A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL"/> |
| - <value value="4" name="A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL"/> |
| - <value value="5" name="A7XX_PERF_RB_STARVE_CYCLES_SP"/> |
| - <value value="6" name="A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE"/> |
| - <value value="7" name="A7XX_PERF_RB_STARVE_CYCLES_CCU"/> |
| - <value value="8" name="A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE"/> |
| - <value value="9" name="A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE"/> |
| - <value value="10" name="A7XX_PERF_RB_Z_WORKLOAD"/> |
| - <value value="11" name="A7XX_PERF_RB_HLSQ_ACTIVE"/> |
| - <value value="12" name="A7XX_PERF_RB_Z_READ"/> |
| - <value value="13" name="A7XX_PERF_RB_Z_WRITE"/> |
| - <value value="14" name="A7XX_PERF_RB_C_READ"/> |
| - <value value="15" name="A7XX_PERF_RB_C_WRITE"/> |
| - <value value="16" name="A7XX_PERF_RB_TOTAL_PASS"/> |
| - <value value="17" name="A7XX_PERF_RB_Z_PASS"/> |
| - <value value="18" name="A7XX_PERF_RB_Z_FAIL"/> |
| - <value value="19" name="A7XX_PERF_RB_S_FAIL"/> |
| - <value value="20" name="A7XX_PERF_RB_BLENDED_FXP_COMPONENTS"/> |
| - <value value="21" name="A7XX_PERF_RB_BLENDED_FP16_COMPONENTS"/> |
| - <value value="22" name="A7XX_PERF_RB_PS_INVOCATIONS"/> |
| - <value value="23" name="A7XX_PERF_RB_2D_ALIVE_CYCLES"/> |
| - <value value="24" name="A7XX_PERF_RB_2D_STALL_CYCLES_A2D"/> |
| - <value value="25" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SRC"/> |
| - <value value="26" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SP"/> |
| - <value value="27" name="A7XX_PERF_RB_2D_STARVE_CYCLES_DST"/> |
| - <value value="28" name="A7XX_PERF_RB_2D_VALID_PIXELS"/> |
| - <value value="29" name="A7XX_PERF_RB_3D_PIXELS"/> |
| - <value value="30" name="A7XX_PERF_RB_BLENDER_WORKING_CYCLES"/> |
| - <value value="31" name="A7XX_PERF_RB_ZPROC_WORKING_CYCLES"/> |
| - <value value="32" name="A7XX_PERF_RB_CPROC_WORKING_CYCLES"/> |
| - <value value="33" name="A7XX_PERF_RB_SAMPLER_WORKING_CYCLES"/> |
| - <value value="34" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> |
| - <value value="35" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> |
| - <value value="36" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> |
| - <value value="37" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> |
| - <value value="38" name="A7XX_PERF_RB_STALL_CYCLES_VPC"/> |
| - <value value="39" name="A7XX_PERF_RB_2D_INPUT_TRANS"/> |
| - <value value="40" name="A7XX_PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> |
| - <value value="41" name="A7XX_PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> |
| - <value value="42" name="A7XX_PERF_RB_BLENDED_FP32_COMPONENTS"/> |
| - <value value="43" name="A7XX_PERF_RB_COLOR_PIX_TILES"/> |
| - <value value="44" name="A7XX_PERF_RB_STALL_CYCLES_CCU"/> |
| - <value value="45" name="A7XX_PERF_RB_EARLY_Z_ARB3_GRANT"/> |
| - <value value="46" name="A7XX_PERF_RB_LATE_Z_ARB3_GRANT"/> |
| - <value value="47" name="A7XX_PERF_RB_EARLY_Z_SKIP_GRANT"/> |
| - <value value="48" name="A7XX_PERF_RB_VRS_1x1_QUADS"/> |
| - <value value="49" name="A7XX_PERF_RB_VRS_2x1_QUADS"/> |
| - <value value="50" name="A7XX_PERF_RB_VRS_1x2_QUADS"/> |
| - <value value="51" name="A7XX_PERF_RB_VRS_2x2_QUADS"/> |
| - <value value="52" name="A7XX_PERF_RB_VRS_4x2_QUADS"/> |
| - <value value="53" name="A7XX_PERF_RB_VRS_4x4_QUADS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_vsc_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_VSC_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_VSC_WORKING_CYCLES"/> |
| - <value value="2" name="A7XX_PERF_VSC_STALL_CYCLES_UCHE"/> |
| - <value value="3" name="A7XX_PERF_VSC_EOT_NUM"/> |
| - <value value="4" name="A7XX_PERF_VSC_INPUT_TILES"/> |
| -</enum> |
| - |
| -<enum name="a7xx_ccu_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_CCU_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> |
| - <value value="2" name="A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> |
| - <value value="3" name="A7XX_PERF_CCU_DEPTH_BLOCKS"/> |
| - <value value="4" name="A7XX_PERF_CCU_COLOR_BLOCKS"/> |
| - <value value="5" name="A7XX_PERF_CCU_DEPTH_BLOCK_HIT"/> |
| - <value value="6" name="A7XX_PERF_CCU_COLOR_BLOCK_HIT"/> |
| - <value value="7" name="A7XX_PERF_CCU_PARTIAL_BLOCK_READ"/> |
| - <value value="8" name="A7XX_PERF_CCU_GMEM_READ"/> |
| - <value value="9" name="A7XX_PERF_CCU_GMEM_WRITE"/> |
| - <value value="10" name="A7XX_PERF_CCU_2D_RD_REQ"/> |
| - <value value="11" name="A7XX_PERF_CCU_2D_WR_REQ"/> |
| - <value value="12" name="A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT"/> |
| - <value value="13" name="A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT"/> |
| - <value value="14" name="A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED"/> |
| - <value value="15" name="A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED"/> |
| - <value value="16" name="A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT"/> |
| - <value value="17" name="A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT"/> |
| - <value value="18" name="A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER"/> |
| - <value value="19" name="A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER"/> |
| - <value value="20" name="A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ"/> |
| - <value value="21" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA"/> |
| - <value value="22" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL"/> |
| -</enum> |
| - |
| -<enum name="a7xx_lrz_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_LRZ_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_LRZ_STARVE_CYCLES_RAS"/> |
| - <value value="2" name="A7XX_PERF_LRZ_STALL_CYCLES_RB"/> |
| - <value value="3" name="A7XX_PERF_LRZ_STALL_CYCLES_VSC"/> |
| - <value value="4" name="A7XX_PERF_LRZ_STALL_CYCLES_VPC"/> |
| - <value value="5" name="A7XX_PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> |
| - <value value="6" name="A7XX_PERF_LRZ_STALL_CYCLES_UCHE"/> |
| - <value value="7" name="A7XX_PERF_LRZ_LRZ_READ"/> |
| - <value value="8" name="A7XX_PERF_LRZ_LRZ_WRITE"/> |
| - <value value="9" name="A7XX_PERF_LRZ_READ_LATENCY"/> |
| - <value value="10" name="A7XX_PERF_LRZ_MERGE_CACHE_UPDATING"/> |
| - <value value="11" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> |
| - <value value="12" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ"/> |
| - <value value="13" name="A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> |
| - <value value="14" name="A7XX_PERF_LRZ_FULL_8X8_TILES"/> |
| - <value value="15" name="A7XX_PERF_LRZ_PARTIAL_8X8_TILES"/> |
| - <value value="16" name="A7XX_PERF_LRZ_TILE_KILLED"/> |
| - <value value="17" name="A7XX_PERF_LRZ_TOTAL_PIXEL"/> |
| - <value value="18" name="A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> |
| - <value value="19" name="A7XX_PERF_LRZ_FEEDBACK_ACCEPT"/> |
| - <value value="20" name="A7XX_PERF_LRZ_FEEDBACK_DISCARD"/> |
| - <value value="21" name="A7XX_PERF_LRZ_FEEDBACK_STALL"/> |
| - <value value="22" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> |
| - <value value="23" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> |
| - <value value="24" name="A7XX_PERF_LRZ_RAS_MASK_TRANS"/> |
| - <value value="25" name="A7XX_PERF_LRZ_STALL_CYCLES_MVC"/> |
| - <value value="26" name="A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS"/> |
| - <value value="27" name="A7XX_PERF_LRZ_TILE_KILLED_BY_Z"/> |
| -</enum> |
| - |
| -<enum name="a7xx_cmp_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB"/> |
| - <value value="1" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> |
| - <value value="2" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> |
| - <value value="3" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> |
| - <value value="4" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> |
| - <value value="5" name="A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST"/> |
| - <value value="6" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> |
| - <value value="7" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA"/> |
| - <value value="8" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA"/> |
| - <value value="9" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> |
| - <value value="10" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> |
| - <value value="11" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> |
| - <value value="12" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> |
| - <value value="13" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> |
| - <value value="14" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> |
| - <value value="15" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> |
| - <value value="16" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> |
| - <value value="17" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> |
| - <value value="18" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> |
| - <value value="19" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> |
| - <value value="20" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> |
| - <value value="21" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> |
| - <value value="22" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> |
| - <value value="23" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> |
| - <value value="24" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> |
| - <value value="25" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> |
| - <value value="26" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> |
| - <value value="27" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> |
| - <value value="28" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> |
| - <value value="29" name="A7XX_PERF_CMPDECMP_RESOLVE_EVENTS"/> |
| - <value value="30" name="A7XX_PERF_CMPDECMP_CONCURRENT_RESOLVE_EVENTS"/> |
| - <value value="31" name="A7XX_PERF_CMPDECMP_DROPPED_CLEAR_EVENTS"/> |
| - <value value="32" name="A7XX_PERF_CMPDECMP_ST_BLOCKS_CONCURRENT"/> |
| - <value value="33" name="A7XX_PERF_CMPDECMP_LRZ_ST_BLOCKS_CONCURRENT"/> |
| - <value value="34" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT"/> |
| - <value value="35" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT"/> |
| - <value value="36" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT"/> |
| - <value value="37" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT"/> |
| - <value value="38" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT"/> |
| - <value value="39" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT"/> |
| - <value value="40" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT"/> |
| - <value value="41" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT"/> |
| - <value value="42" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT"/> |
| - <value value="43" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT"/> |
| - <value value="44" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT"/> |
| - <value value="45" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT"/> |
| - <value value="46" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT"/> |
| - <value value="47" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT"/> |
| - <value value="48" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT"/> |
| - <value value="49" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT"/> |
| -</enum> |
| - |
| -<enum name="a7xx_gbif_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_GBIF_RESERVED_0"/> |
| - <value value="1" name="A7XX_PERF_GBIF_RESERVED_1"/> |
| - <value value="2" name="A7XX_PERF_GBIF_RESERVED_2"/> |
| - <value value="3" name="A7XX_PERF_GBIF_RESERVED_3"/> |
| - <value value="4" name="A7XX_PERF_GBIF_RESERVED_4"/> |
| - <value value="5" name="A7XX_PERF_GBIF_RESERVED_5"/> |
| - <value value="6" name="A7XX_PERF_GBIF_RESERVED_6"/> |
| - <value value="7" name="A7XX_PERF_GBIF_RESERVED_7"/> |
| - <value value="8" name="A7XX_PERF_GBIF_RESERVED_8"/> |
| - <value value="9" name="A7XX_PERF_GBIF_RESERVED_9"/> |
| - <value value="10" name="A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL"/> |
| - <value value="11" name="A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL"/> |
| - <value value="12" name="A7XX_PERF_GBIF_RESERVED_12"/> |
| - <value value="13" name="A7XX_PERF_GBIF_RESERVED_13"/> |
| - <value value="14" name="A7XX_PERF_GBIF_RESERVED_14"/> |
| - <value value="15" name="A7XX_PERF_GBIF_RESERVED_15"/> |
| - <value value="16" name="A7XX_PERF_GBIF_RESERVED_16"/> |
| - <value value="17" name="A7XX_PERF_GBIF_RESERVED_17"/> |
| - <value value="18" name="A7XX_PERF_GBIF_RESERVED_18"/> |
| - <value value="19" name="A7XX_PERF_GBIF_RESERVED_19"/> |
| - <value value="20" name="A7XX_PERF_GBIF_RESERVED_20"/> |
| - <value value="21" name="A7XX_PERF_GBIF_RESERVED_21"/> |
| - <value value="22" name="A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL"/> |
| - <value value="23" name="A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL"/> |
| - <value value="24" name="A7XX_PERF_GBIF_RESERVED_24"/> |
| - <value value="25" name="A7XX_PERF_GBIF_RESERVED_25"/> |
| - <value value="26" name="A7XX_PERF_GBIF_RESERVED_26"/> |
| - <value value="27" name="A7XX_PERF_GBIF_RESERVED_27"/> |
| - <value value="28" name="A7XX_PERF_GBIF_RESERVED_28"/> |
| - <value value="29" name="A7XX_PERF_GBIF_RESERVED_29"/> |
| - <value value="30" name="A7XX_PERF_GBIF_RESERVED_30"/> |
| - <value value="31" name="A7XX_PERF_GBIF_RESERVED_31"/> |
| - <value value="32" name="A7XX_PERF_GBIF_RESERVED_32"/> |
| - <value value="33" name="A7XX_PERF_GBIF_RESERVED_33"/> |
| - <value value="34" name="A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL"/> |
| - <value value="35" name="A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL"/> |
| - <value value="36" name="A7XX_PERF_GBIF_RESERVED_36"/> |
| - <value value="37" name="A7XX_PERF_GBIF_RESERVED_37"/> |
| - <value value="38" name="A7XX_PERF_GBIF_RESERVED_38"/> |
| - <value value="39" name="A7XX_PERF_GBIF_RESERVED_39"/> |
| - <value value="40" name="A7XX_PERF_GBIF_RESERVED_40"/> |
| - <value value="41" name="A7XX_PERF_GBIF_RESERVED_41"/> |
| - <value value="42" name="A7XX_PERF_GBIF_RESERVED_42"/> |
| - <value value="43" name="A7XX_PERF_GBIF_RESERVED_43"/> |
| - <value value="44" name="A7XX_PERF_GBIF_RESERVED_44"/> |
| - <value value="45" name="A7XX_PERF_GBIF_RESERVED_45"/> |
| - <value value="46" name="A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL"/> |
| - <value value="47" name="A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL"/> |
| - <value value="48" name="A7XX_PERF_GBIF_RESERVED_48"/> |
| - <value value="49" name="A7XX_PERF_GBIF_RESERVED_49"/> |
| - <value value="50" name="A7XX_PERF_GBIF_RESERVED_50"/> |
| - <value value="51" name="A7XX_PERF_GBIF_RESERVED_51"/> |
| - <value value="52" name="A7XX_PERF_GBIF_RESERVED_52"/> |
| - <value value="53" name="A7XX_PERF_GBIF_RESERVED_53"/> |
| - <value value="54" name="A7XX_PERF_GBIF_RESERVED_54"/> |
| - <value value="55" name="A7XX_PERF_GBIF_RESERVED_55"/> |
| - <value value="56" name="A7XX_PERF_GBIF_RESERVED_56"/> |
| - <value value="57" name="A7XX_PERF_GBIF_RESERVED_57"/> |
| - <value value="58" name="A7XX_PERF_GBIF_RESERVED_58"/> |
| - <value value="59" name="A7XX_PERF_GBIF_RESERVED_59"/> |
| - <value value="60" name="A7XX_PERF_GBIF_RESERVED_60"/> |
| - <value value="61" name="A7XX_PERF_GBIF_RESERVED_61"/> |
| - <value value="62" name="A7XX_PERF_GBIF_RESERVED_62"/> |
| - <value value="63" name="A7XX_PERF_GBIF_RESERVED_63"/> |
| - <value value="64" name="A7XX_PERF_GBIF_RESERVED_64"/> |
| - <value value="65" name="A7XX_PERF_GBIF_RESERVED_65"/> |
| - <value value="66" name="A7XX_PERF_GBIF_RESERVED_66"/> |
| - <value value="67" name="A7XX_PERF_GBIF_RESERVED_67"/> |
| - <value value="68" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL"/> |
| - <value value="69" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL"/> |
| - <value value="70" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL"/> |
| - <value value="71" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL"/> |
| - <value value="72" name="A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF"/> |
| - <value value="73" name="A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF"/> |
| - <value value="74" name="A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF"/> |
| - <value value="75" name="A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF"/> |
| - <value value="76" name="A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF"/> |
| - <value value="77" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF"/> |
| - <value value="78" name="A7XX_PERF_GBIF_AXI_ALL_READ_BEATS"/> |
| - <value value="79" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_BEATS"/> |
| - <value value="80" name="A7XX_PERF_GBIF_AXI_ALL_BEATS"/> |
| -</enum> |
| - |
| -<enum name="a7xx_ufc_perfcounter_select"> |
| - <value value="0" name="A7XX_PERF_UFC_BUSY_CYCLES"/> |
| - <value value="1" name="A7XX_PERF_UFC_READ_DATA_VBIF"/> |
| - <value value="2" name="A7XX_PERF_UFC_WRITE_DATA_VBIF"/> |
| - <value value="3" name="A7XX_PERF_UFC_READ_REQUEST_VBIF"/> |
| - <value value="4" name="A7XX_PERF_UFC_WRITE_REQUEST_VBIF"/> |
| - <value value="5" name="A7XX_PERF_UFC_LRZ_FILTER_HIT"/> |
| - <value value="6" name="A7XX_PERF_UFC_LRZ_FILTER_MISS"/> |
| - <value value="7" name="A7XX_PERF_UFC_CRE_FILTER_HIT"/> |
| - <value value="8" name="A7XX_PERF_UFC_CRE_FILTER_MISS"/> |
| - <value value="9" name="A7XX_PERF_UFC_SP_FILTER_HIT"/> |
| - <value value="10" name="A7XX_PERF_UFC_SP_FILTER_MISS"/> |
| - <value value="11" name="A7XX_PERF_UFC_SP_REQUESTS"/> |
| - <value value="12" name="A7XX_PERF_UFC_TP_FILTER_HIT"/> |
| - <value value="13" name="A7XX_PERF_UFC_TP_FILTER_MISS"/> |
| - <value value="14" name="A7XX_PERF_UFC_TP_REQUESTS"/> |
| - <value value="15" name="A7XX_PERF_UFC_MAIN_HIT_LRZ_PREFETCH"/> |
| - <value value="16" name="A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH"/> |
| - <value value="17" name="A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH"/> |
| - <value value="18" name="A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH"/> |
| - <value value="19" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_READ"/> |
| - <value value="20" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE"/> |
| - <value value="21" name="A7XX_PERF_UFC_MAIN_MISS_LRZ_PREFETCH"/> |
| - <value value="22" name="A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH"/> |
| - <value value="23" name="A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH"/> |
| - <value value="24" name="A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH"/> |
| - <value value="25" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_READ"/> |
| - <value value="26" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE"/> |
| - <value value="27" name="A7XX_PERF_UFC_UBWC_READ_UFC_TRANS"/> |
| - <value value="28" name="A7XX_PERF_UFC_UBWC_WRITE_UFC_TRANS"/> |
| - <value value="29" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD"/> |
| - <value value="30" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA"/> |
| - <value value="31" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA"/> |
| - <value value="32" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG"/> |
| - <value value="33" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN"/> |
| - <value value="34" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT"/> |
| - <value value="35" name="A7XX_PERF_UFC_LRZ_PREFETCH_STALLED_CYCLES"/> |
| - <value value="36" name="A7XX_PERF_UFC_CRE_PREFETCH_STALLED_CYCLES"/> |
| - <value value="37" name="A7XX_PERF_UFC_SPTP_PREFETCH_STALLED_CYCLES"/> |
| - <value value="38" name="A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES"/> |
| - <value value="39" name="A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES"/> |
| - <value value="40" name="A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES"/> |
| - <value value="41" name="A7XX_PERF_UFC_EVICTION_STALLED_CYCLES"/> |
| - <value value="42" name="A7XX_PERF_UFC_LOCK_STALLED_CYCLES"/> |
| - <value value="43" name="A7XX_PERF_UFC_MISS_LATENCY_CYCLES"/> |
| - <value value="44" name="A7XX_PERF_UFC_MISS_LATENCY_SAMPLES"/> |
| - <value value="45" name="A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES"/> |
| - <value value="46" name="A7XX_PERF_UFC_TP_HINT_TAG_MISS"/> |
| - <value value="47" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_RDY"/> |
| - <value value="48" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_NRDY"/> |
| - <value value="49" name="A7XX_PERF_UFC_TP_HINT_IS_FCLEAR"/> |
| - <value value="50" name="A7XX_PERF_UFC_TP_HINT_IS_ALPHA0"/> |
| - <value value="51" name="A7XX_PERF_UFC_SP_L1_FILTER_HIT"/> |
| - <value value="52" name="A7XX_PERF_UFC_SP_L1_FILTER_MISS"/> |
| - <value value="53" name="A7XX_PERF_UFC_SP_L1_FILTER_REQUESTS"/> |
| - <value value="54" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_RDY"/> |
| - <value value="55" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_NRDY"/> |
| - <value value="56" name="A7XX_PERF_UFC_TP_L1_TAG_MISS"/> |
| - <value value="57" name="A7XX_PERF_UFC_TP_L1_FILTER_REQUESTS"/> |
| -</enum> |
| - |
| <domain name="A6XX" width="32" prefix="variant" varset="chip"> |
| <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip"> |
| <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/> |
| @@ -2371,7 +177,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/> |
| <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/> |
| <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/> |
| - <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/> |
| + <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE"/> |
| <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> |
| <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> |
| <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> |
| @@ -2400,22 +206,22 @@ to upconvert to 32b float internally? |
| --> |
| <reg64 offset="0x0934" name="CP_VSD_BASE"/> |
| |
| - <bitset name="a6xx_roq_stat" inline="yes"> |
| + <bitset name="a6xx_roq_status" inline="yes"> |
| <bitfield name="RPTR" low="0" high="9"/> |
| <bitfield name="WPTR" low="16" high="25"/> |
| </bitset> |
| - <reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/> |
| - <reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/> |
| - <reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/> |
| - <reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/> |
| - <reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/> |
| - <reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/> |
| - |
| - <reg32 offset="0x0943" name="CP_IB1_DWORDS"/> |
| - <reg32 offset="0x0944" name="CP_IB2_DWORDS"/> |
| - <reg32 offset="0x0945" name="CP_SDS_DWORDS"/> |
| - <reg32 offset="0x0946" name="CP_MRB_DWORDS"/> |
| - <reg32 offset="0x0947" name="CP_VSD_DWORDS"/> |
| + <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status"/> |
| + <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status"/> |
| + <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status"/> |
| + <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status"/> |
| + <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status"/> |
| + <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status"/> |
| + |
| + <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE"/> |
| + <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE"/> |
| + <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE"/> |
| + <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE"/> |
| + <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE"/> |
| |
| <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB"> |
| <doc>number of remaining dwords incl current dword being consumed?</doc> |
| @@ -2451,6 +257,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x098D" name="CP_AHB_CNTL"/> |
| <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/> |
| <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/> |
| + <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/> |
| <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/> |
| <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/> |
| |
| @@ -2468,8 +275,8 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/> |
| <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/> |
| |
| - <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/> |
| - <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/> |
| + <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX-"/> |
| + <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX-"/> |
| <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/> |
| <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/> |
| |
| @@ -2619,28 +426,17 @@ to upconvert to 32b float internally? |
| vertices in, number of primnitives assembled etc. |
| --> |
| |
| - <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in --> |
| - <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/> |
| - <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out --> |
| - <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/> |
| - <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in --> |
| - <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/> |
| - <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out --> |
| - <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/> |
| - <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in --> |
| - <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/> |
| - <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out --> |
| - <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/> |
| - <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in --> |
| - <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/> |
| - <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out --> |
| - <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/> |
| - <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out --> |
| - <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/> |
| - <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in --> |
| - <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/> |
| - <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/> |
| - <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/> |
| + <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES"/> |
| + <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES"/> |
| + <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS"/> |
| + <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS"/> |
| + <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS"/> |
| + <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS"/> |
| + <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES"/> |
| + <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS"/> |
| + <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES"/> |
| + <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS"/> |
| + <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS"/> |
| |
| <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> |
| <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> |
| @@ -2779,7 +575,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/> |
| <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/> |
| <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/> |
| - <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/> |
| + <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/> |
| <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-"> |
| <bitfield name="TXDONE" pos="0" type="boolean"/> |
| </reg32> |
| @@ -2840,7 +636,7 @@ to upconvert to 32b float internally? |
| </reg32> |
| <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> |
| <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> |
| - <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> |
| + <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2" variants="A6XX"/> |
| <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX"> |
| <doc> |
| Set to true when binning, isn't changed afterwards |
| @@ -2936,8 +732,8 @@ to upconvert to 32b float internally? |
| <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> |
| <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/> |
| </reg32> |
| - <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/> |
| - <reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit"> |
| + <reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/> |
| + <reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="rp_blit"> |
| <bitfield name="NX" low="1" high="10" type="uint"/> |
| <bitfield name="NY" low="11" high="20" type="uint"/> |
| </reg32> |
| @@ -2967,14 +763,14 @@ to upconvert to 32b float internally? |
| |
| LIMIT is set to PITCH - 64, to make room for a bit of overflow |
| --> |
| - <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/> |
| - <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/> |
| - <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/> |
| - <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/> |
| - <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/> |
| - <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/> |
| - |
| - <array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit"> |
| + <reg64 offset="0x0c30" name="VSC_PIPE_DATA_PRIM_BASE" type="waddress" usage="cmd"/> |
| + <reg32 offset="0x0c32" name="VSC_PIPE_DATA_PRIM_STRIDE" usage="cmd"/> |
| + <reg32 offset="0x0c33" name="VSC_PIPE_DATA_PRIM_LENGTH" usage="cmd"/> |
| + <reg64 offset="0x0c34" name="VSC_PIPE_DATA_DRAW_BASE" type="waddress" usage="cmd"/> |
| + <reg32 offset="0x0c36" name="VSC_PIPE_DATA_DRAW_STRIDE" usage="cmd"/> |
| + <reg32 offset="0x0c37" name="VSC_PIPE_DATA_DRAW_LENGTH" usage="cmd"/> |
| + |
| + <array offset="0x0c38" name="VSC_CHANNEL_VISIBILITY" stride="1" length="32" usage="rp_blit"> |
| <doc> |
| Seems to be a bitmap of which tiles mapped to the VSC |
| pipe contain geometry. |
| @@ -2985,7 +781,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x0" name="REG"/> |
| </array> |
| |
| - <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> |
| + <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> |
| <doc> |
| Has the size of data written to corresponding VSC_PRIM_STRM |
| buffer. |
| @@ -2993,10 +789,10 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x0" name="REG"/> |
| </array> |
| |
| - <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> |
| + <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> |
| <doc> |
| Has the size of data written to corresponding VSC pipe, ie. |
| - same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI |
| + same thing that is written out to VSC_SIZE_BASE |
| </doc> |
| <reg32 offset="0x0" name="REG"/> |
| </array> |
| @@ -3028,17 +824,17 @@ to upconvert to 32b float internally? |
| <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> |
| </reg32> |
| |
| - <bitset name="a6xx_gras_xs_cl_cntl" inline="yes"> |
| + <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> |
| <bitfield name="CLIP_MASK" low="0" high="7"/> |
| <bitfield name="CULL_MASK" low="8" high="15"/> |
| </bitset> |
| - <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> |
| + <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> |
| + <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> |
| + <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit"/> |
| |
| - <reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit"> |
| - <!-- see also RB_RENDER_CONTROL0 --> |
| + <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" usage="rp_blit"> |
| + <!-- see also RB_INTERP_CNTL --> |
| <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> |
| <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> |
| <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> |
| @@ -3067,7 +863,7 @@ to upconvert to 32b float internally? |
| <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> |
| |
| <!-- 0x8006-0x800f invalid --> |
| - <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit"> |
| + <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" usage="rp_blit"> |
| <reg32 offset="0" name="XOFFSET" type="float"/> |
| <reg32 offset="1" name="XSCALE" type="float"/> |
| <reg32 offset="2" name="YOFFSET" type="float"/> |
| @@ -3075,7 +871,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="4" name="ZOFFSET" type="float"/> |
| <reg32 offset="5" name="ZSCALE" type="float"/> |
| </array> |
| - <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit"> |
| + <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" usage="rp_blit"> |
| <reg32 offset="0" name="MIN" type="float"/> |
| <reg32 offset="1" name="MAX" type="float"/> |
| </array> |
| @@ -3124,7 +920,12 @@ to upconvert to 32b float internally? |
| |
| <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd"> |
| <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> |
| - <bitfield name="SHIFTAMOUNT" low="1" high="2"/> |
| + <enum name="a6xx_shift_amount"> |
| + <value value="0" name="NO_SHIFT"/> |
| + <value value="1" name="HALF_PIXEL_SHIFT"/> |
| + <value value="2" name="FULL_PIXEL_SHIFT"/> |
| + </enum> |
| + <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/> |
| <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> |
| <bitfield name="UNK4" low="4" high="5"/> |
| </reg32> |
| @@ -3133,13 +934,13 @@ to upconvert to 32b float internally? |
| <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> |
| </reg32> |
| |
| - <bitset name="a6xx_gras_layer_cntl" inline="yes"> |
| + <bitset name="a6xx_gras_us_xs_siv_cntl" inline="yes"> |
| <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> |
| <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> |
| </bitset> |
| - <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> |
| <!-- 0x809e/0x809f invalid --> |
| |
| <enum name="a6xx_sequenced_thread_dist"> |
| @@ -3213,13 +1014,13 @@ to upconvert to 32b float internally? |
| <enum name="a6xx_lrz_feedback_mask"> |
| <value value="0x0" name="LRZ_FEEDBACK_NONE"/> |
| <value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/> |
| - <value value="0x2" name="LRZ_FEEDBACK_EARLY_LRZ_LATE_Z"/> |
| + <value value="0x2" name="LRZ_FEEDBACK_EARLY_Z_LATE_Z"/> |
| <!-- We don't have a flag type and this flags combination is often used --> |
| - <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z"/> |
| + <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z"/> |
| <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/> |
| </enum> |
| |
| - <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit"> |
| + <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" usage="rp_blit"> |
| <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> |
| <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> |
| <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> |
| @@ -3235,22 +1036,22 @@ to upconvert to 32b float internally? |
| <bitfield name="UNK27" pos="27"/> |
| </reg32> |
| |
| - <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" usage="rp_blit"> |
| <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> |
| <bitfield name="UNK2" pos="2"/> |
| <bitfield name="UNK3" pos="3"/> |
| </reg32> |
| - <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" usage="rp_blit"> |
| <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> |
| <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> |
| </reg32> |
| |
| - <bitset name="a6xx_sample_config" inline="yes"> |
| + <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> |
| <bitfield name="UNK0" pos="0"/> |
| <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/> |
| </bitset> |
| |
| - <bitset name="a6xx_sample_locations" inline="yes"> |
| + <bitset name="a6xx_programmable_msaa_pos" inline="yes"> |
| <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/> |
| <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/> |
| <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/> |
| @@ -3261,9 +1062,9 @@ to upconvert to 32b float internally? |
| <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> |
| </bitset> |
| |
| - <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> |
| - <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> |
| - <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> |
| + <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> |
| + <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> |
| |
| <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/> |
| |
| @@ -3286,13 +1087,36 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> |
| <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> |
| |
| - <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate --> |
| - <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/> |
| - <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/> |
| - <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/> |
| - <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/> |
| - <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/> |
| - <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/> |
| + <enum name="a6xx_fsr_combiner"> |
| + <value value="0" name="FSR_COMBINER_OP_KEEP"/> |
| + <value value="1" name="FSR_COMBINER_OP_REPLACE"/> |
| + <value value="2" name="FSR_COMBINER_OP_MIN"/> |
| + <value value="3" name="FSR_COMBINER_OP_MAX"/> |
| + <value value="4" name="FSR_COMBINER_OP_MUL"/> |
| + </enum> |
| + |
| + <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> |
| + <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/> |
| + <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/> |
| + <bitfield name="COMBINER_OP_1" low="5" high="7" type="a6xx_fsr_combiner"/> |
| + <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/> |
| + <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/> |
| + <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/> |
| + </reg32> |
| + <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="LAYERED" pos="0" type="boolean"/> |
| + <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/> |
| + </reg32> |
| + <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="WIDTH" low="0" high="15" type="uint"/> |
| + <bitfield name="HEIGHT" low="16" high="31" type="uint"/> |
| + </reg32> |
| + <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX-" type="waddress" usage="rp_blit"/> |
| + <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> |
| + <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/> |
| + </reg32> |
| |
| <enum name="a6xx_lrz_dir_status"> |
| <value value="0x1" name="LRZ_DIR_LE"/> |
| @@ -3313,7 +1137,7 @@ to upconvert to 32b float internally? |
| </doc> |
| <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/> |
| <!-- set when depth-test + depth-write enabled --> |
| - <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/> |
| + <bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/> |
| <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> |
| <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/> |
| <doc> |
| @@ -3339,14 +1163,13 @@ to upconvert to 32b float internally? |
| <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> |
| </reg32> |
| |
| - <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit"> |
| + <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" usage="rp_blit"> |
| <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> |
| </reg32> |
| <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/> |
| <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit"> |
| - <!-- TODO: fix the shr fields --> |
| <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> |
| - <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/> |
| + <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/> |
| </reg32> |
| |
| <!-- |
| @@ -3381,18 +1204,18 @@ to upconvert to 32b float internally? |
| --> |
| <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/> |
| <!-- 0x8108 invalid --> |
| - <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> |
| <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> |
| </reg32> |
| <!-- |
| LRZ buffer represents a single array layer + mip level, and there is |
| a single buffer per depth image. Thus to reuse LRZ between renderpasses |
| it is necessary to track the depth view used in the past renderpass, which |
| - GRAS_LRZ_DEPTH_VIEW is for. |
| - GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to |
| + GRAS_LRZ_VIEW_INFO is for. |
| + GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_VIEW_INFO is equal to |
| the value stored in the LRZ buffer, if not - LRZ is disabled. |
| --> |
| - <reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd"> |
| + <reg32 offset="0x810a" name="GRAS_LRZ_VIEW_INFO" usage="cmd"> |
| <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/> |
| <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/> |
| <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/> |
| @@ -3408,7 +1231,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/> |
| |
| <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> |
| - <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/> |
| + <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX-"/> |
| |
| <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> |
| @@ -3430,7 +1253,7 @@ to upconvert to 32b float internally? |
| <value value="0x5" name="ROTATE_VFLIP"/> |
| </enum> |
| |
| - <bitset name="a6xx_2d_blit_cntl" inline="yes"> |
| + <bitset name="a6xx_a2d_bit_cntl" inline="yes"> |
| <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> |
| <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> |
| <bitfield name="UNK4" low="4" high="6"/> |
| @@ -3447,22 +1270,22 @@ to upconvert to 32b float internally? |
| <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/> |
| </bitset> |
| |
| - <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> |
| <!-- note: the low 8 bits for src coords are valid, probably fixed point |
| it would be a bit weird though, since we subtract 1 from BR coords |
| apparently signed, gallium driver uses negative coords and it works? |
| --> |
| - <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/> |
| - <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/> |
| - <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/> |
| - <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/> |
| - <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/> |
| - <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/> |
| + <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" usage="rp_blit"/> |
| + <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" usage="rp_blit"/> |
| + <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" usage="rp_blit"/> |
| + <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" usage="rp_blit"/> |
| + <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" usage="rp_blit"/> |
| + <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" usage="rp_blit"/> |
| <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> |
| <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> |
| <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> |
| - <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> |
| - <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> |
| + <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> |
| + <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> |
| <!-- 0x840c-0x85ff invalid --> |
| |
| <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> |
| @@ -3481,7 +1304,7 @@ to upconvert to 32b float internally? |
| --> |
| |
| <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> |
| - <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX" usage="rp_blit"> |
| <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> |
| <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> |
| <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> |
| @@ -3490,7 +1313,7 @@ to upconvert to 32b float internally? |
| <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> |
| </reg32> |
| |
| - <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x8800" name="RB_CNTL" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> |
| <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> |
| <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> |
| @@ -3501,8 +1324,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> |
| <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> |
| <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> |
| - <!-- set during binning pass: --> |
| - <bitfield name="BINNING" pos="7" type="boolean"/> |
| + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> |
| <bitfield name="UNK8" low="8" high="10"/> |
| <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> |
| <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> |
| @@ -3515,15 +1337,14 @@ to upconvert to 32b float internally? |
| </reg32> |
| <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> |
| - <!-- set during binning pass: --> |
| - <bitfield name="BINNING" pos="7" type="boolean"/> |
| + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> |
| <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> |
| <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> |
| <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> |
| <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> |
| </reg32> |
| <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> |
| - <bitfield name="BINNING" pos="7" type="boolean"/> |
| + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> |
| </reg32> |
| |
| <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit"> |
| @@ -3536,16 +1357,16 @@ to upconvert to 32b float internally? |
| <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> |
| </reg32> |
| |
| - <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> |
| - <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> |
| - <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> |
| + <reg32 offset="0x8804" name="RB_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x8805" name="RB_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> |
| + <reg32 offset="0x8806" name="RB_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> |
| <!-- 0x8807-0x8808 invalid --> |
| <!-- |
| note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL |
| name comes from kernel and is probably right) |
| --> |
| - <reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit"> |
| - <!-- see also GRAS_CNTL --> |
| + <reg32 offset="0x8809" name="RB_INTERP_CNTL" usage="rp_blit"> |
| + <!-- see also GRAS_CL_INTERP_CNTL --> |
| <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> |
| <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> |
| <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> |
| @@ -3555,7 +1376,7 @@ to upconvert to 32b float internally? |
| <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> |
| <bitfield name="UNK10" pos="10" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit"> |
| + <reg32 offset="0x880a" name="RB_PS_INPUT_CNTL" usage="rp_blit"> |
| <!-- enable bits for various FS sysvalue regs: --> |
| <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> |
| <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/> |
| @@ -3567,16 +1388,16 @@ to upconvert to 32b float internally? |
| <bitfield name="FOVEATION" pos="8" type="boolean"/> |
| </reg32> |
| |
| - <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit"> |
| + <reg32 offset="0x880b" name="RB_PS_OUTPUT_CNTL" usage="rp_blit"> |
| <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> |
| <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> |
| <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> |
| <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit"> |
| + <reg32 offset="0x880c" name="RB_PS_MRT_CNTL" usage="rp_blit"> |
| <bitfield name="MRT" low="0" high="3" type="uint"/> |
| </reg32> |
| - <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit"> |
| + <reg32 offset="0x880d" name="RB_PS_OUTPUT_MASK" usage="rp_blit"> |
| <bitfield name="RT0" low="0" high="3"/> |
| <bitfield name="RT1" low="4" high="7"/> |
| <bitfield name="RT2" low="8" high="11"/> |
| @@ -3608,7 +1429,7 @@ to upconvert to 32b float internally? |
| <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> |
| </reg32> |
| |
| - <reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x8810" name="RB_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> |
| <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> |
| </reg32> |
| <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/> |
| @@ -3672,18 +1493,18 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/> |
| </array> |
| |
| - <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/> |
| - <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/> |
| - <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/> |
| - <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/> |
| - <reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd"> |
| + <reg32 offset="0x8860" name="RB_BLEND_CONSTANT_RED_FP32" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x8861" name="RB_BLEND_CONSTANT_GREEN_FP32" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x8862" name="RB_BLEND_CONSTANT_BLUE_FP32" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x8863" name="RB_BLEND_CONSTANT_ALPHA_FP32" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x8864" name="RB_ALPHA_TEST_CNTL" usage="cmd"> |
| <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> |
| <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> |
| <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> |
| </reg32> |
| <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit"> |
| <!-- per-mrt enable bit --> |
| - <bitfield name="ENABLE_BLEND" low="0" high="7"/> |
| + <bitfield name="BLEND_READS_DEST" low="0" high="7"/> |
| <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> |
| <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> |
| <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> |
| @@ -3726,12 +1547,12 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/> |
| <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/> |
| <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> |
| + <reg32 offset="0x8877" name="RB_DEPTH_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> |
| |
| - <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/> |
| - <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x8878" name="RB_DEPTH_BOUND_MIN" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x8879" name="RB_DEPTH_BOUND_MAX" type="float" usage="rp_blit"/> |
| <!-- 0x887a-0x887f invalid --> |
| - <reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit"> |
| + <reg32 offset="0x8880" name="RB_STENCIL_CNTL" usage="rp_blit"> |
| <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> |
| <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> |
| <!-- |
| @@ -3753,11 +1574,11 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit"> |
| <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A6XX" usage="rp_blit"> |
| <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> |
| <bitfield name="UNK1" pos="1" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> |
| <bitfield name="UNK1" pos="1" type="boolean"/> |
| <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/> |
| @@ -3765,22 +1586,22 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/> |
| <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/> |
| <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> |
| - <reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit"> |
| + <reg32 offset="0x8886" name="RB_STENCIL_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> |
| + <reg32 offset="0x8887" name="RB_STENCIL_REF_CNTL" usage="rp_blit"> |
| <bitfield name="REF" low="0" high="7"/> |
| <bitfield name="BFREF" low="8" high="15"/> |
| </reg32> |
| - <reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit"> |
| + <reg32 offset="0x8888" name="RB_STENCIL_MASK" usage="rp_blit"> |
| <bitfield name="MASK" low="0" high="7"/> |
| <bitfield name="BFMASK" low="8" high="15"/> |
| </reg32> |
| - <reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit"> |
| + <reg32 offset="0x8889" name="RB_STENCIL_WRITE_MASK" usage="rp_blit"> |
| <bitfield name="WRMASK" low="0" high="7"/> |
| <bitfield name="BFWRMASK" low="8" high="15"/> |
| </reg32> |
| <!-- 0x888a-0x888f invalid --> |
| <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> |
| - <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd"> |
| + <reg32 offset="0x8891" name="RB_SAMPLE_COUNTER_CNTL" usage="cmd"> |
| <bitfield name="DISABLE" pos="0" type="boolean"/> |
| <bitfield name="COPY" pos="1" type="boolean"/> |
| </reg32> |
| @@ -3791,27 +1612,27 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/> |
| <!-- 0x8899-0x88bf invalid --> |
| <!-- clamps depth value for depth test/write --> |
| - <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/> |
| - <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit"/> |
| + <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit"/> |
| <!-- 0x88c2-0x88cf invalid--> |
| - <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit"> |
| + <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit"> |
| <bitfield name="UNK0" low="0" high="12"/> |
| <bitfield name="UNK16" low="16" high="26"/> |
| </reg32> |
| - <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> |
| - <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> |
| + <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> |
| + <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> |
| <!-- weird to duplicate other regs from same block?? --> |
| - <reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit"> |
| + <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" usage="rp_blit"> |
| <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> |
| <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> |
| </reg32> |
| - <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/> |
| - <reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x88d4" name="RB_RESOLVE_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> |
| + <reg32 offset="0x88d5" name="RB_RESOLVE_GMEM_BUFFER_INFO" usage="rp_blit"> |
| <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> |
| </reg32> |
| - <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> |
| + <reg32 offset="0x88d6" name="RB_RESOLVE_GMEM_BUFFER_BASE" low="12" high="31" shr="12" usage="rp_blit"/> |
| <!-- s/DST_FORMAT/DST_INFO/ probably: --> |
| - <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit"> |
| + <reg32 offset="0x88d7" name="RB_RESOLVE_SYSTEM_BUFFER_INFO" usage="rp_blit"> |
| <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> |
| <bitfield name="FLAGS" pos="2" type="boolean"/> |
| <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> |
| @@ -3820,25 +1641,31 @@ to upconvert to 32b float internally? |
| <bitfield name="UNK15" pos="15" type="boolean"/> |
| <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> |
| </reg32> |
| - <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0x88d8" name="RB_RESOLVE_SYSTEM_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> |
| + <reg32 offset="0x88da" name="RB_RESOLVE_SYSTEM_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> |
| <!-- array-pitch is size of layer --> |
| - <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> |
| - <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit"> |
| + <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0x88dc" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> |
| + <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" usage="rp_blit"> |
| <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> |
| <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> |
| </reg32> |
| |
| - <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/> |
| - <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/> |
| - <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/> |
| - <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/> |
| + <reg32 offset="0x88df" name="RB_RESOLVE_CLEAR_COLOR_DW0" usage="rp_blit"/> |
| + <reg32 offset="0x88e0" name="RB_RESOLVE_CLEAR_COLOR_DW1" usage="rp_blit"/> |
| + <reg32 offset="0x88e1" name="RB_RESOLVE_CLEAR_COLOR_DW2" usage="rp_blit"/> |
| + <reg32 offset="0x88e2" name="RB_RESOLVE_CLEAR_COLOR_DW3" usage="rp_blit"/> |
| + |
| + <enum name="a6xx_blit_event_type"> |
| + <value value="0x0" name="BLIT_EVENT_STORE"/> |
| + <value value="0x1" name="BLIT_EVENT_STORE_AND_CLEAR"/> |
| + <value value="0x2" name="BLIT_EVENT_CLEAR"/> |
| + <value value="0x3" name="BLIT_EVENT_LOAD"/> |
| + </enum> |
| |
| <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> |
| - <reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit"> |
| - <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? --> |
| - <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? --> |
| + <reg32 offset="0x88e3" name="RB_RESOLVE_OPERATION" usage="rp_blit"> |
| + <bitfield name="TYPE" low="0" high="1" type="a6xx_blit_event_type"/> |
| <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> |
| <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> |
| <doc> |
| @@ -3853,16 +1680,20 @@ to upconvert to 32b float internally? |
| <!-- set when this is the last resolve on a650+ --> |
| <bitfield name="LAST" low="8" high="9"/> |
| <!-- |
| - a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil. |
| - a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise. |
| - |
| - We believe this is related to concurrent resolves |
| + a618 GLES: color render target number being resolved for CCU_RESOLVE, 0x8 for depth, 0x9 for separate stencil. |
| + a618 VK: 0x8 for depth CCU_RESOLVE, 0x9 for separate stencil, 0 otherwise. |
| + a7xx VK: 0x8 for depth, 0x9 for separate stencil, 0x0 to 0x7 used for concurrent resolves of color render |
| + targets inside a given resolve group. |
| --> |
| <bitfield name="BUFFER_ID" low="12" high="15"/> |
| </reg32> |
| - <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit"> |
| - <!-- Value conditioned based on predicate, changed before blits --> |
| - <bitfield name="UNK0" pos="0" type="boolean"/> |
| + |
| + <enum name="a7xx_blit_clear_mode"> |
| + <value value="0x0" name="CLEAR_MODE_SYSMEM"/> |
| + <value value="0x1" name="CLEAR_MODE_GMEM"/> |
| + </enum> |
| + <reg32 offset="0x88e4" name="RB_CLEAR_TARGET" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="CLEAR_MODE" pos="0" type="a7xx_blit_clear_mode"/> |
| </reg32> |
| |
| <enum name="a6xx_ccu_cache_size"> |
| @@ -3871,7 +1702,7 @@ to upconvert to 32b float internally? |
| <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/> |
| <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/> |
| </enum> |
| - <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd"> |
| + <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX-" usage="cmd"> |
| <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/> |
| <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/> |
| <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> |
| @@ -3895,7 +1726,13 @@ to upconvert to 32b float internally? |
| <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> |
| <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/> |
| </reg32> |
| - <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/> |
| + |
| + <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit"> |
| + <bitfield name="UNK2" pos="2" type="boolean"/> |
| + <bitfield name="PIPELINE_FSR_ENABLE" pos="4" type="boolean"/> |
| + <bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/> |
| + <bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/> |
| + </reg32> |
| <!-- Connected to VK_EXT_fragment_density_map? --> |
| <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/> |
| <!-- 0x88f6-0x88ff invalid --> |
| @@ -3906,7 +1743,7 @@ to upconvert to 32b float internally? |
| <bitfield name="UNK8" low="8" high="10"/> |
| <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> |
| </reg32> |
| - <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> |
| + <array offset="0x8903" name="RB_COLOR_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> |
| <reg64 offset="0" name="ADDR" type="waddress" align="64"/> |
| <reg32 offset="2" name="PITCH"> |
| <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> |
| @@ -3915,10 +1752,10 @@ to upconvert to 32b float internally? |
| </array> |
| <!-- 0x891b-0x8926 invalid --> |
| <doc> |
| - RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. After that |
| + RB_SAMPLE_COUNTER_BASE register is used up to (and including) a730. After that |
| the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. |
| </doc> |
| - <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd"/> |
| + <reg64 offset="0x8927" name="RB_SAMPLE_COUNTER_BASE" type="waddress" align="16" usage="cmd"/> |
| <!-- 0x8929-0x89ff invalid --> |
| |
| <!-- TODO: there are some registers in the 0x8a00-0x8bff range --> |
| @@ -3932,10 +1769,10 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/> |
| <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/> |
| |
| - <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/> |
| + <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="rp_blit"/> |
| |
| - <bitset name="a6xx_2d_src_surf_info" inline="yes"> |
| + <bitset name="a6xx_a2d_src_texture_info" inline="yes"> |
| <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> |
| <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> |
| <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> |
| @@ -3954,7 +1791,7 @@ to upconvert to 32b float internally? |
| <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/> |
| </bitset> |
| |
| - <bitset name="a6xx_2d_dst_surf_info" inline="yes"> |
| + <bitset name="a6xx_a2d_dest_buffer_info" inline="yes"> |
| <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> |
| <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> |
| <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> |
| @@ -3965,26 +1802,26 @@ to upconvert to 32b float internally? |
| </bitset> |
| |
| <!-- 0x8c02-0x8c16 invalid --> |
| - <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_dst_surf_info" usage="rp_blit"/> |
| - <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0x8c17" name="RB_A2D_DEST_BUFFER_INFO" type="a6xx_a2d_dest_buffer_info" usage="rp_blit"/> |
| + <reg64 offset="0x8c18" name="RB_A2D_DEST_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> |
| + <reg32 offset="0x8c1a" name="RB_A2D_DEST_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> |
| <!-- this is a guess but seems likely (for NV12/IYUV): --> |
| - <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> |
| - <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/> |
| + <reg64 offset="0x8c1b" name="RB_A2D_DEST_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> |
| + <reg32 offset="0x8c1d" name="RB_A2D_DEST_BUFFER_PITCH_1" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0x8c1e" name="RB_A2D_DEST_BUFFER_BASE_2" type="waddress" align="64" usage="rp_blit"/> |
| |
| - <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0x8c20" name="RB_A2D_DEST_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> |
| + <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> |
| <!-- this is a guess but seems likely (for NV12 with UBWC): --> |
| - <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/> |
| - <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0x8c23" name="RB_A2D_DEST_FLAG_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> |
| + <reg32 offset="0x8c25" name="RB_A2D_DEST_FLAG_BUFFER_PITCH_1" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> |
| |
| <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers --> |
| <!-- unlike a5xx, these are per channel values rather than packed --> |
| - <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/> |
| - <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/> |
| - <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/> |
| - <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/> |
| + <reg32 offset="0x8c2c" name="RB_A2D_CLEAR_COLOR_DW0" usage="rp_blit"/> |
| + <reg32 offset="0x8c2d" name="RB_A2D_CLEAR_COLOR_DW1" usage="rp_blit"/> |
| + <reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="rp_blit"/> |
| + <reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="rp_blit"/> |
| |
| <reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/> |
| |
| @@ -3996,7 +1833,7 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff --> |
| <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> |
| <!-- 0x02080000 in GMEM, zero otherwise? --> |
| - <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0x8e06" name="RB_CCU_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> |
| |
| <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX"> |
| <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> |
| @@ -4017,10 +1854,21 @@ to upconvert to 32b float internally? |
| <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> |
| <!--TODO: valid mask 0xfffffc1f --> |
| </reg32> |
| + <enum name="a7xx_concurrent_resolve_mode"> |
| + <value value="0x0" name="CONCURRENT_RESOLVE_MODE_DISABLED"/> |
| + <value value="0x1" name="CONCURRENT_RESOLVE_MODE_1"/> |
| + <value value="0x2" name="CONCURRENT_RESOLVE_MODE_2"/> |
| + </enum> |
| + <enum name="a7xx_concurrent_unresolve_mode"> |
| + <value value="0x0" name="CONCURRENT_UNRESOLVE_MODE_DISABLED"/> |
| + <value value="0x1" name="CONCURRENT_UNRESOLVE_MODE_PARTIAL"/> |
| + <value value="0x3" name="CONCURRENT_UNRESOLVE_MODE_FULL"/> |
| + </enum> |
| <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-"> |
| <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> |
| - <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> |
| - <!-- rest of the bits were moved to RB_CCU_CNTL2 --> |
| + <bitfield name="CONCURRENT_RESOLVE_MODE" low="2" high="3" type="a7xx_concurrent_resolve_mode"/> |
| + <bitfield name="CONCURRENT_UNRESOLVE_MODE" low="5" high="6" type="a7xx_concurrent_unresolve_mode"/> |
| + <!-- rest of the bits were moved to RB_CCU_CACHE_CNTL --> |
| </reg32> |
| <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"> |
| <bitfield name="MODE" pos="0" type="boolean"/> |
| @@ -4046,9 +1894,9 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> |
| <!-- 0x8e3e-0x8e4f invalid --> |
| <!-- GMEM save/restore for preemption: --> |
| - <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/> |
| + <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/> |
| <!-- address for GMEM save/restore? --> |
| - <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/> |
| + <reg32 offset="0x8e51" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR" type="waddress" align="1"/> |
| <!-- 0x8e53-0x8e7f invalid --> |
| <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/> |
| <!-- 0x8e80-0x8e83 are valid --> |
| @@ -4069,38 +1917,38 @@ to upconvert to 32b float internally? |
| <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> |
| <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> |
| </bitset> |
| - <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| |
| - <reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> |
| |
| - <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes"> |
| + <bitset name="a6xx_vpc_xs_siv_cntl" inline="yes"> |
| <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> |
| <bitfield name="VIEWLOC" low="8" high="15" type="uint"/> |
| <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> |
| </bitset> |
| |
| - <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> |
| |
| - <reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> |
| |
| <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> |
| - <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused --> |
| + <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> |
| <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> |
| <bitfield name="UNK2" pos="2" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit"> |
| + <reg32 offset="0x9108" name="VPC_RAST_CNTL" usage="rp_blit"> |
| <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> |
| </reg32> |
| |
| - <bitset name="a6xx_primitive_cntl_0" inline="yes"> |
| + <bitset name="a6xx_pc_cntl" inline="yes"> |
| <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> |
| <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> |
| <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean"> |
| @@ -4113,7 +1961,7 @@ to upconvert to 32b float internally? |
| <bitfield name="UNK3" pos="3" type="boolean"/> |
| </bitset> |
| |
| - <bitset name="a6xx_primitive_cntl_5" inline="yes"> |
| + <bitset name="a6xx_gs_param_0" inline="yes"> |
| <doc> |
| geometry shader |
| </doc> |
| @@ -4125,7 +1973,7 @@ to upconvert to 32b float internally? |
| <bitfield name="UNK18" pos="18"/> |
| </bitset> |
| |
| - <bitset name="a6xx_multiview_cntl" inline="yes"> |
| + <bitset name="a6xx_stereo_rendering_cntl" inline="yes"> |
| <bitfield name="ENABLE" pos="0" type="boolean"/> |
| <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean"> |
| <doc> |
| @@ -4139,10 +1987,10 @@ to upconvert to 32b float internally? |
| <bitfield name="VIEWS" low="2" high="6" type="uint"/> |
| </bitset> |
| |
| - <reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX-" usage="rp_blit"/> |
| |
| <enum name="a6xx_varying_interp_mode"> |
| <value value="0" name="INTERP_SMOOTH"/> |
| @@ -4159,11 +2007,11 @@ to upconvert to 32b float internally? |
| </enum> |
| |
| <!-- 0x9109-0x91ff invalid --> |
| - <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit"> |
| + <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" usage="rp_blit"> |
| <doc>Packed array of a6xx_varying_interp_mode</doc> |
| <reg32 offset="0x0" name="MODE"/> |
| </array> |
| - <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit"> |
| + <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE_0" stride="1" length="8" usage="rp_blit"> |
| <doc>Packed array of a6xx_varying_ps_repl_mode</doc> |
| <reg32 offset="0x0" name="MODE"/> |
| </array> |
| @@ -4172,12 +2020,12 @@ to upconvert to 32b float internally? |
| <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> |
| <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> |
| |
| - <array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit"> |
| + <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL_0" stride="1" length="4" usage="rp_blit"> |
| <!-- one bit per varying component: --> |
| <reg32 offset="0" name="DISABLE"/> |
| </array> |
| |
| - <reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" usage="rp_blit"> |
| <!-- |
| Choose which DWORD to write to. There is an array of |
| (4 * 64) DWORD's, dumped in the devcoredump at |
| @@ -4198,7 +2046,7 @@ to upconvert to 32b float internally? |
| When EmitStreamVertex(N) happens, the HW goes to DWORD |
| 64 * N and then "executes" the next 64 DWORD's. |
| |
| - This field is auto-incremented when VPC_SO_PROG is |
| + This field is auto-incremented when VPC_SO_MAPPING_PORT is |
| written to. |
| --> |
| <bitfield name="ADDR" low="0" high="7" type="hex"/> |
| @@ -4206,7 +2054,7 @@ to upconvert to 32b float internally? |
| <bitfield name="RESET" pos="16" type="boolean"/> |
| </reg32> |
| <!-- special register, write multiple times to load SO program (not readable) --> |
| - <reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit"> |
| + <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" usage="rp_blit"> |
| <bitfield name="A_BUF" low="0" high="1" type="uint"/> |
| <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> |
| <bitfield name="A_EN" pos="11" type="boolean"/> |
| @@ -4215,7 +2063,7 @@ to upconvert to 32b float internally? |
| <bitfield name="B_EN" pos="23" type="boolean"/> |
| </reg32> |
| |
| - <reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/> |
| + <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" usage="cmd"/> |
| |
| <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd"> |
| <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> |
| @@ -4225,14 +2073,14 @@ to upconvert to 32b float internally? |
| <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> |
| </array> |
| |
| - <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd"> |
| + <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" usage="cmd"> |
| <bitfield name="INVERT" pos="0" type="boolean"/> |
| </reg32> |
| <!-- 0x9237-0x92ff invalid --> |
| <!-- always 0x0 ? --> |
| <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/> |
| |
| - <bitset name="a6xx_vpc_xs_pack" inline="yes"> |
| + <bitset name="a6xx_vpc_xs_cntl" inline="yes"> |
| <doc> |
| num of varyings plus four for gl_Position (plus one if gl_PointSize) |
| plus # of transform-feedback (streamout) varyings if using the |
| @@ -4249,11 +2097,11 @@ to upconvert to 32b float internally? |
| </doc> |
| </bitfield> |
| </bitset> |
| - <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> |
| - <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> |
| - <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> |
| + <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> |
| |
| - <reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit"> |
| + <reg32 offset="0x9304" name="VPC_PS_CNTL" usage="rp_blit"> |
| <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> |
| <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> |
| <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> |
| @@ -4272,7 +2120,7 @@ to upconvert to 32b float internally? |
| </bitfield> |
| </reg32> |
| |
| - <reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x9305" name="VPC_SO_CNTL" usage="rp_blit"> |
| <!-- |
| It's offset by 1, and 0 means "disabled" |
| --> |
| @@ -4282,19 +2130,19 @@ to upconvert to 32b float internally? |
| <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> |
| <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> |
| </reg32> |
| - <reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit"> |
| + <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" usage="rp_blit"> |
| <bitfield name="DISABLE" pos="0" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" variants="A6XX-" usage="rp_blit"> <!-- A702 + A7xx --> |
| <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> |
| </reg32> |
| - <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="SIZE_GMEM" low="0" high="31"/> |
| </reg32> |
| - <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="BASE_GMEM" low="0" high="31"/> |
| </reg32> |
| - <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="SIZE_GMEM" low="0" high="31"/> |
| </reg32> |
| |
| @@ -4311,15 +2159,15 @@ to upconvert to 32b float internally? |
| <!-- TODO: regs from 0x9624-0x963a --> |
| <!-- 0x963b-0x97ff invalid --> |
| |
| - <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" usage="rp_blit"/> |
| |
| <!-- always 0x0 ? --> |
| - <reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit"> |
| + <reg32 offset="0x9801" name="PC_HS_PARAM_1" usage="rp_blit"> |
| <bitfield name="SIZE" low="0" high="10" type="uint"/> |
| <bitfield name="UNK13" pos="13"/> |
| </reg32> |
| |
| - <reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x9802" name="PC_DS_PARAM" usage="rp_blit"> |
| <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> |
| <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> |
| </reg32> |
| @@ -4334,7 +2182,7 @@ to upconvert to 32b float internally? |
| </reg32> |
| |
| <!-- New in a6xx gen3+ --> |
| - <reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit"> |
| + <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" usage="rp_blit"> |
| <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> |
| </reg32> |
| |
| @@ -4344,15 +2192,15 @@ to upconvert to 32b float internally? |
| <!-- 0x980b-0x983f invalid --> |
| |
| <!-- 0x9840 - 0x9842 are not readable --> |
| - <reg32 offset="0x9840" name="PC_DRAW_CMD"> |
| + <reg32 offset="0x9840" name="PC_DRAW_INITIATOR"> |
| <bitfield name="STATE_ID" low="0" high="7"/> |
| </reg32> |
| |
| - <reg32 offset="0x9841" name="PC_DISPATCH_CMD"> |
| + <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR"> |
| <bitfield name="STATE_ID" low="0" high="7"/> |
| </reg32> |
| |
| - <reg32 offset="0x9842" name="PC_EVENT_CMD"> |
| + <reg32 offset="0x9842" name="PC_EVENT_INITIATOR"> |
| <!-- I think only the low bit is actually used? --> |
| <bitfield name="STATE_ID" low="16" high="23"/> |
| <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> |
| @@ -4367,27 +2215,27 @@ to upconvert to 32b float internally? |
| |
| <!-- 0x9843-0x997f invalid --> |
| |
| - <reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" variants="A6XX" usage="rp_blit"> |
| <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> |
| </reg32> |
| - <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> |
| </reg32> |
| |
| - <reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" variants="A6XX" usage="rp_blit"> |
| <!-- which stream to send to GRAS --> |
| <bitfield name="STREAM" low="0" high="1" type="uint"/> |
| <!-- discard primitives before rasterization --> |
| <bitfield name="DISCARD" pos="2" type="boolean"/> |
| </reg32> |
| - <!-- VPC_RASTER_CNTL --> |
| - <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit"> |
| + <!-- VPC_RAST_STREAM_CNTL --> |
| + <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" variants="A7XX-" usage="rp_blit"> |
| <!-- which stream to send to GRAS --> |
| <bitfield name="STREAM" low="0" high="1" type="uint"/> |
| <!-- discard primitives before rasterization --> |
| <bitfield name="DISCARD" pos="2" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" variants="A7XX-" usage="rp_blit"> |
| <!-- which stream to send to GRAS --> |
| <bitfield name="STREAM" low="0" high="1" type="uint"/> |
| <!-- discard primitives before rasterization --> |
| @@ -4397,17 +2245,17 @@ to upconvert to 32b float internally? |
| <!-- Both are a750+. |
| Probably needed to correctly overlap execution of several draws. |
| --> |
| - <reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> |
| <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of |
| this additional space is not known. |
| --> |
| - <reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> |
| |
| <!-- 0x9982-0x9aff invalid --> |
| |
| - <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/> |
| + <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" usage="rp_blit"/> |
| |
| - <bitset name="a6xx_xs_out_cntl" inline="yes"> |
| + <bitset name="a6xx_pc_xs_cntl" inline="yes"> |
| <doc> |
| num of varyings plus four for gl_Position (plus one if gl_PointSize) |
| plus # of transform-feedback (streamout) varyings if using the |
| @@ -4417,19 +2265,19 @@ to upconvert to 32b float internally? |
| <bitfield name="PSIZE" pos="8" type="boolean"/> |
| <bitfield name="LAYER" pos="9" type="boolean"/> |
| <bitfield name="VIEW" pos="10" type="boolean"/> |
| - <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit --> |
| + <!-- note: PC_VS_CNTL doesn't have the PRIMITIVE_ID bit --> |
| <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> |
| <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> |
| <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> |
| </bitset> |
| |
| - <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> |
| <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> |
| - <reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> |
| - <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> |
| |
| - <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/> |
| + <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" usage="rp_blit"/> |
| |
| <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> |
| <doc> |
| @@ -4438,9 +2286,9 @@ to upconvert to 32b float internally? |
| <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> |
| </reg32> |
| |
| - <reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/> |
| + <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> |
| <!-- mask of enabled views, doesn't exist on A630 --> |
| - <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/> |
| + <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" usage="rp_blit"/> |
| <!-- 0x9b09-0x9bff invalid --> |
| <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> |
| <!-- special register (but note first 8 bits can be written/read) --> |
| @@ -4451,31 +2299,31 @@ to upconvert to 32b float internally? |
| <!-- TODO: 0x9e00-0xa000 range incomplete --> |
| <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> |
| <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> |
| - <reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/> |
| - <reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/> |
| - <reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/> |
| - <reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage="cmd"/> |
| - <reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage="cmd"/> |
| + <reg64 offset="0x9e04" name="PC_DMA_BASE"/> |
| + <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint"/> |
| + <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint"/> |
| + <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> |
| + <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX-" type="waddress" align="32" usage="cmd"/> |
| |
| - <reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx"> |
| + <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx"> |
| <doc> |
| Possibly not really "initiating" the draw but the layout is similar |
| to VGT_DRAW_INITIATOR on older gens |
| </doc> |
| </reg32> |
| - <reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/> |
| - <reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/> |
| + <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint"/> |
| + <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint"/> |
| |
| <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> |
| - <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL"> |
| + <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL"> |
| <bitfield name="UNK0" low="0" high="15"/> |
| <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> |
| <bitfield name="VSC_N" low="22" high="26" type="uint"/> |
| </reg32> |
| - <reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/> |
| - <reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/> |
| + <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32"/> |
| + <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32"/> |
| |
| - <reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE"> |
| + <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE"> |
| <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> |
| <bitfield name="OVERRIDE" pos="0" type="boolean"/> |
| </reg32> |
| @@ -4488,18 +2336,18 @@ to upconvert to 32b float internally? |
| <!-- always 0x0 --> |
| <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/> |
| |
| - <reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit"> |
| + <reg32 offset="0xa000" name="VFD_CNTL_0" usage="rp_blit"> |
| <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> |
| <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit"> |
| + <reg32 offset="0xa001" name="VFD_CNTL_1" usage="rp_blit"> |
| <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> |
| <!-- only used for VS in non-multi-position-output case --> |
| <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit"> |
| + <reg32 offset="0xa002" name="VFD_CNTL_2" usage="rp_blit"> |
| <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid"> |
| <doc> |
| This is the ID of the current patch within the |
| @@ -4512,32 +2360,32 @@ to upconvert to 32b float internally? |
| </bitfield> |
| <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit"> |
| + <reg32 offset="0xa003" name="VFD_CNTL_3" usage="rp_blit"> |
| <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit"> |
| + <reg32 offset="0xa004" name="VFD_CNTL_4" usage="rp_blit"> |
| <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit"> |
| + <reg32 offset="0xa005" name="VFD_CNTL_5" usage="rp_blit"> |
| <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit"> |
| + <reg32 offset="0xa006" name="VFD_CNTL_6" usage="rp_blit"> |
| <!-- |
| True if gl_PrimitiveID is read via the FS |
| --> |
| <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/> |
| </reg32> |
| |
| - <reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd"> |
| + <reg32 offset="0xa007" name="VFD_RENDER_MODE" usage="cmd"> |
| <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/> |
| </reg32> |
| |
| - <reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/> |
| - <reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd"> |
| + <reg32 offset="0xa008" name="VFD_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> |
| + <reg32 offset="0xa009" name="VFD_MODE_CNTL" usage="cmd"> |
| <!-- add VFD_INDEX_OFFSET to REGID4VTX --> |
| <bitfield name="VERTEX" pos="0" type="boolean"/> |
| <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> |
| @@ -4546,14 +2394,14 @@ to upconvert to 32b float internally? |
| |
| <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/> |
| <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/> |
| - <array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit"> |
| + <array offset="0xa010" name="VFD_VERTEX_BUFFER" stride="4" length="32" usage="rp_blit"> |
| <reg64 offset="0x0" name="BASE" type="address" align="1"/> |
| <reg32 offset="0x2" name="SIZE" type="uint"/> |
| <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/> |
| </array> |
| - <array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit"> |
| + <array offset="0xa090" name="VFD_FETCH_INSTR" stride="2" length="32" usage="rp_blit"> |
| <reg32 offset="0x0" name="INSTR"> |
| - <!-- IDX and byte OFFSET into VFD_FETCH --> |
| + <!-- IDX and byte OFFSET into VFD_VERTEX_BUFFER --> |
| <bitfield name="IDX" low="0" high="4" type="uint"/> |
| <bitfield name="OFFSET" low="5" high="16"/> |
| <bitfield name="INSTANCED" pos="17" type="boolean"/> |
| @@ -4573,7 +2421,7 @@ to upconvert to 32b float internally? |
| |
| <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/> |
| |
| - <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> |
| |
| <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/> |
| <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/> |
| @@ -4588,7 +2436,7 @@ to upconvert to 32b float internally? |
| <value value="1" name="THREAD128"/> |
| </enum> |
| |
| - <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes"> |
| + <bitset name="a6xx_sp_xs_cntl_0" inline="yes"> |
| <!-- if set to SINGLE, only use 1 concurrent wave on each SP --> |
| <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> |
| <!-- |
| @@ -4620,7 +2468,7 @@ to upconvert to 32b float internally? |
| --> |
| <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/> |
| <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/> |
| - <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/> |
| + <bitfield name="BINDLESS_UAV" pos="2" type="boolean"/> |
| <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/> |
| |
| <bitfield name="ENABLED" pos="8" type="boolean"/> |
| @@ -4630,17 +2478,17 @@ to upconvert to 32b float internally? |
| --> |
| <bitfield name="NTEX" low="9" high="16" type="uint"/> |
| <bitfield name="NSAMP" low="17" high="21" type="uint"/> |
| - <bitfield name="NIBO" low="22" high="28" type="uint"/> |
| + <bitfield name="NUAV" low="22" high="28" type="uint"/> |
| </bitset> |
| |
| - <bitset name="a6xx_sp_xs_prim_cntl" inline="yes"> |
| + <bitset name="a6xx_sp_xs_output_cntl" inline="yes"> |
| <!-- # of VS outputs including pos/psize --> |
| <bitfield name="OUT" low="0" high="5" type="uint"/> |
| <!-- FLAGS_REGID only for GS --> |
| <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> |
| </bitset> |
| |
| - <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> |
| + <reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> |
| <!-- |
| This field actually controls all geometry stages. TCS, TES, and |
| GS must have the same mergedregs setting as VS. |
| @@ -4665,10 +2513,10 @@ to upconvert to 32b float internally? |
| </reg32> |
| <!-- bitmask of true/false conditions for VS brac.N instructions, |
| bit N corresponds to brac.N --> |
| - <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/> |
| + <reg32 offset="0xa801" name="SP_VS_BOOLEAN_CF_MASK" type="hex"/> |
| <!-- # of VS outputs including pos/psize --> |
| - <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> |
| - <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit"> |
| + <reg32 offset="0xa802" name="SP_VS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> |
| + <array offset="0xa803" name="SP_VS_OUTPUT" stride="1" length="16" usage="rp_blit"> |
| <reg32 offset="0x0" name="REG"> |
| <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> |
| @@ -4678,12 +2526,12 @@ to upconvert to 32b float internally? |
| </array> |
| <!-- |
| Starting with a5xx, position/psize outputs from shader end up in the |
| - SP_VS_OUT map, with highest OUTLOCn position. (Generally they are |
| + SP_VS_OUTPUT map, with highest OUTLOCn position. (Generally they are |
| the last entries too, except when gl_PointCoord is used, blob inserts |
| an extra varying after, but with a lower OUTLOC position. If present, |
| psize is last, preceded by position. |
| --> |
| - <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit"> |
| + <array offset="0xa813" name="SP_VS_VPC_DEST" stride="1" length="8" usage="rp_blit"> |
| <reg32 offset="0x0" name="REG"> |
| <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> |
| <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> |
| @@ -4752,7 +2600,7 @@ to upconvert to 32b float internally? |
| </bitfield> |
| </bitset> |
| |
| - <bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes"> |
| + <bitset name="a6xx_sp_xs_pvt_mem_stack_offset" inline="yes"> |
| <doc> |
| This seems to be be the equivalent of HWSTACKOFFSET in |
| a3xx. The ldp/stp offset formula above isn't affected by |
| @@ -4763,18 +2611,18 @@ to upconvert to 32b float internally? |
| <bitfield name="OFFSET" low="0" high="18" shr="11"/> |
| </bitset> |
| |
| - <reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> |
| - <reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/> |
| + <reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> |
| - <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> |
| + <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> |
| - <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa822" name="SP_VS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> |
| <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> |
| - <reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> |
| - <reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> |
| - <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> |
| + <reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/> |
| |
| - <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> |
| + <reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> |
| <!-- There is no mergedregs bit, that comes from the VS. --> |
| <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> |
| </reg32> |
| @@ -4782,32 +2630,32 @@ to upconvert to 32b float internally? |
| Total size of local storage in dwords divided by the wave size. |
| The maximum value is 64. With the wave size being always 64 for HS, |
| the maximum size of local storage should be: |
| - 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k |
| + 64 (wavesize) * 64 (SP_HS_CNTL_1) * 4 = 16k |
| --> |
| - <reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/> |
| - <reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/> |
| + <reg32 offset="0xa831" name="SP_HS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa832" name="SP_HS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> |
| |
| <!-- TODO: exact same layout as 0xa81b-0xa825 --> |
| - <reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> |
| - <reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/> |
| + <reg32 offset="0xa833" name="SP_HS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0xa834" name="SP_HS_BASE" type="address" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> |
| - <reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> |
| + <reg64 offset="0xa837" name="SP_HS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> |
| - <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa83a" name="SP_HS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> |
| <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> |
| - <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> |
| - <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> |
| - <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> |
| + <reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/> |
| |
| - <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> |
| + <reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> |
| <!-- There is no mergedregs bit, that comes from the VS. --> |
| <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/> |
| + <reg32 offset="0xa841" name="SP_DS_BOOLEAN_CF_MASK" type="hex"/> |
| |
| <!-- TODO: exact same layout as 0xa802-0xa81a --> |
| - <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> |
| - <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit"> |
| + <reg32 offset="0xa842" name="SP_DS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> |
| + <array offset="0xa843" name="SP_DS_OUTPUT" stride="1" length="16" usage="rp_blit"> |
| <reg32 offset="0x0" name="REG"> |
| <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> |
| @@ -4815,7 +2663,7 @@ to upconvert to 32b float internally? |
| <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> |
| </reg32> |
| </array> |
| - <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit"> |
| + <array offset="0xa853" name="SP_DS_VPC_DEST" stride="1" length="8" usage="rp_blit"> |
| <reg32 offset="0x0" name="REG"> |
| <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> |
| <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> |
| @@ -4825,22 +2673,22 @@ to upconvert to 32b float internally? |
| </array> |
| |
| <!-- TODO: exact same layout as 0xa81b-0xa825 --> |
| - <reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> |
| - <reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/> |
| + <reg32 offset="0xa85b" name="SP_DS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0xa85c" name="SP_DS_BASE" type="address" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> |
| - <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> |
| + <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> |
| - <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa862" name="SP_DS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> |
| <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> |
| - <reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> |
| - <reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> |
| - <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> |
| + <reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/> |
| |
| - <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> |
| + <reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> |
| <!-- There is no mergedregs bit, that comes from the VS. --> |
| <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit"> |
| + <reg32 offset="0xa871" name="SP_GS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"> |
| <doc> |
| Normally the size of the output of the last stage in |
| dwords. It should be programmed as follows: |
| @@ -4854,11 +2702,11 @@ to upconvert to 32b float internally? |
| doesn't matter in practice. |
| </doc> |
| </reg32> |
| - <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/> |
| + <reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> |
| |
| <!-- TODO: exact same layout as 0xa802-0xa81a --> |
| - <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> |
| - <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit"> |
| + <reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> |
| + <array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="rp_blit"> |
| <reg32 offset="0x0" name="REG"> |
| <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> |
| @@ -4867,7 +2715,7 @@ to upconvert to 32b float internally? |
| </reg32> |
| </array> |
| |
| - <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit"> |
| + <array offset="0xa884" name="SP_GS_VPC_DEST" stride="1" length="8" usage="rp_blit"> |
| <reg32 offset="0x0" name="REG"> |
| <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> |
| <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> |
| @@ -4877,29 +2725,29 @@ to upconvert to 32b float internally? |
| </array> |
| |
| <!-- TODO: exact same layout as 0xa81b-0xa825 --> |
| - <reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> |
| - <reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/> |
| + <reg32 offset="0xa88c" name="SP_GS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0xa88d" name="SP_GS_BASE" type="address" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> |
| - <reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> |
| + <reg64 offset="0xa890" name="SP_GS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> |
| <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> |
| - <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa893" name="SP_GS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> |
| <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> |
| - <reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> |
| - <reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> |
| - <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> |
| - |
| - <reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/> |
| - <reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/> |
| - <reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/> |
| - <reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/> |
| - <reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/> |
| - <reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/> |
| - <reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/> |
| - <reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/> |
| + <reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> |
| + <reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/> |
| + |
| + <reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> |
| + <reg64 offset="0xa8a2" name="SP_HS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> |
| + <reg64 offset="0xa8a4" name="SP_DS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> |
| + <reg64 offset="0xa8a6" name="SP_GS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> |
| + <reg64 offset="0xa8a8" name="SP_VS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> |
| + <reg64 offset="0xa8aa" name="SP_HS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> |
| + <reg64 offset="0xa8ac" name="SP_DS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> |
| + <reg64 offset="0xa8ae" name="SP_GS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> |
| |
| <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 --> |
| |
| - <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> |
| + <reg32 offset="0xa980" name="SP_PS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> |
| <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> |
| <bitfield name="UNK21" pos="21" type="boolean"/> |
| <bitfield name="VARYING" pos="22" type="boolean"/> |
| @@ -4909,8 +2757,7 @@ to upconvert to 32b float internally? |
| fine derivatives and quad subgroup ops. |
| </doc> |
| </bitfield> |
| - <!-- note: vk blob uses bit24 --> |
| - <bitfield name="UNK24" pos="24" type="boolean"/> |
| + <bitfield name="INOUTREGOVERLAP" pos="24" type="boolean"/> |
| <bitfield name="UNK25" pos="25" type="boolean"/> |
| <bitfield name="PIXLODENABLE" pos="26" type="boolean"> |
| <doc> |
| @@ -4923,12 +2770,12 @@ to upconvert to 32b float internally? |
| <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/> |
| <bitfield name="MERGEDREGS" pos="31" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/> |
| - <reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> |
| - <reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/> |
| - <reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> |
| - <reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> |
| - <reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> |
| + <reg32 offset="0xa981" name="SP_PS_BOOLEAN_CF_MASK" type="hex"/> |
| + <reg32 offset="0xa982" name="SP_PS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> |
| + <reg64 offset="0xa983" name="SP_PS_BASE" type="address" align="32" usage="rp_blit"/> |
| + <reg32 offset="0xa985" name="SP_PS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> |
| + <reg64 offset="0xa986" name="SP_PS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> |
| + <reg32 offset="0xa988" name="SP_PS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> |
| |
| <reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit"> |
| <!-- per-mrt enable bit --> |
| @@ -4948,7 +2795,7 @@ to upconvert to 32b float internally? |
| <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> |
| <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit"> |
| + <reg32 offset="0xa98b" name="SP_PS_OUTPUT_MASK" usage="rp_blit"> |
| <bitfield name="RT0" low="0" high="3"/> |
| <bitfield name="RT1" low="4" high="7"/> |
| <bitfield name="RT2" low="8" high="11"/> |
| @@ -4958,17 +2805,17 @@ to upconvert to 32b float internally? |
| <bitfield name="RT6" low="24" high="27"/> |
| <bitfield name="RT7" low="28" high="31"/> |
| </reg32> |
| - <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit"> |
| + <reg32 offset="0xa98c" name="SP_PS_OUTPUT_CNTL" usage="rp_blit"> |
| <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> |
| <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit"> |
| + <reg32 offset="0xa98d" name="SP_PS_MRT_CNTL" usage="rp_blit"> |
| <bitfield name="MRT" low="0" high="3" type="uint"/> |
| </reg32> |
| |
| - <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit"> |
| + <array offset="0xa98e" name="SP_PS_OUTPUT" stride="1" length="8" usage="rp_blit"> |
| <doc>per MRT</doc> |
| <reg32 offset="0x0" name="REG"> |
| <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> |
| @@ -4976,7 +2823,7 @@ to upconvert to 32b float internally? |
| </reg32> |
| </array> |
| |
| - <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit"> |
| + <array offset="0xa996" name="SP_PS_MRT" stride="1" length="8" usage="rp_blit"> |
| <reg32 offset="0" name="REG"> |
| <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> |
| <bitfield name="COLOR_SINT" pos="8" type="boolean"/> |
| @@ -4985,7 +2832,7 @@ to upconvert to 32b float internally? |
| </reg32> |
| </array> |
| |
| - <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit"> |
| + <reg32 offset="0xa99e" name="SP_PS_INITIAL_TEX_LOAD_CNTL" usage="rp_blit"> |
| <bitfield name="COUNT" low="0" high="2" type="uint"/> |
| <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/> |
| <doc> |
| @@ -5002,7 +2849,7 @@ to upconvert to 32b float internally? |
| <!-- Blob never uses it --> |
| <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/> |
| </reg32> |
| - <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit"> |
| + <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A6XX" usage="rp_blit"> |
| <reg32 offset="0" name="CMD" variants="A6XX"> |
| <bitfield name="SRC" low="0" high="6" type="uint"/> |
| <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> |
| @@ -5016,7 +2863,7 @@ to upconvert to 32b float internally? |
| <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/> |
| </reg32> |
| </array> |
| - <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit"> |
| + <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A7XX-" usage="rp_blit"> |
| <reg32 offset="0" name="CMD" variants="A7XX-"> |
| <bitfield name="SRC" low="0" high="6" type="uint"/> |
| <bitfield name="SAMP_ID" low="7" high="9" type="uint"/> |
| @@ -5028,22 +2875,23 @@ to upconvert to 32b float internally? |
| <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/> |
| </reg32> |
| </array> |
| - <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit"> |
| + <array offset="0xa9a3" name="SP_PS_INITIAL_TEX_INDEX" stride="1" length="4" usage="rp_blit"> |
| <reg32 offset="0" name="CMD"> |
| <bitfield name="SAMP_ID" low="0" high="15" type="uint"/> |
| <bitfield name="TEX_ID" low="16" high="31" type="uint"/> |
| </reg32> |
| </array> |
| - <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> |
| <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? --> |
| - <reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> |
| + <reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> |
| + <reg32 offset="0xa9ab" name="SP_PS_UNKNOWN_A9AB" variants="A7XX-" usage="cmd"/> |
| |
| <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> |
| |
| |
| |
| |
| - <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd"> |
| + <reg32 offset="0xa9b0" name="SP_CS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="cmd"> |
| <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> |
| <!-- seems to make SP use less concurrent threads when possible? --> |
| <bitfield name="UNK21" pos="21" type="boolean"/> |
| @@ -5053,8 +2901,15 @@ to upconvert to 32b float internally? |
| <bitfield name="MERGEDREGS" pos="31" type="boolean"/> |
| </reg32> |
| |
| + <enum name="a6xx_const_ram_mode"> |
| + <value value="0x0" name="CONSTLEN_128"/> |
| + <value value="0x1" name="CONSTLEN_192"/> |
| + <value value="0x2" name="CONSTLEN_256"/> |
| + <value value="0x3" name="CONSTLEN_512"/> <!-- a7xx only --> |
| + </enum> |
| + |
| <!-- set for compute shaders --> |
| - <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd"> |
| + <reg32 offset="0xa9b1" name="SP_CS_CNTL_1" usage="cmd"> |
| <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"> |
| <doc> |
| If 0 - all 32k of shared storage is enabled, otherwise |
| @@ -5065,32 +2920,36 @@ to upconvert to 32b float internally? |
| always return 0) |
| </doc> |
| </bitfield> |
| - <bitfield name="UNK5" pos="5" type="boolean"/> |
| - <!-- always 1 ? --> |
| - <bitfield name="UNK6" pos="6" type="boolean"/> |
| + <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"> |
| + <doc> |
| + This defines the split between consts and local |
| + memory in the Local Buffer. The programmed value |
| + must be at least the actual CONSTLEN. |
| + </doc> |
| + </bitfield> |
| </reg32> |
| - <reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/> |
| - <reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/> |
| - <reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/> |
| + <reg32 offset="0xa9b2" name="SP_CS_BOOLEAN_CF_MASK" type="hex" usage="cmd"/> |
| + <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/> |
| + <reg64 offset="0xa9b4" name="SP_CS_BASE" type="address" align="32" usage="cmd"/> |
| <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/> |
| - <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/> |
| + <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" align="32" usage="cmd"/> |
| <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/> |
| - <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/> |
| + <reg32 offset="0xa9ba" name="SP_CS_TSIZE" low="0" high="7" type="uint" usage="cmd"/> |
| <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> |
| - <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/> |
| - <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="cmd"/> |
| + <reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="cmd"/> |
| + <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="cmd"/> |
| <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/> |
| - <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/> |
| |
| - <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 --> |
| - <reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd"> |
| + <!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 --> |
| + <reg32 offset="0xa9c2" name="SP_CS_WIE_CNTL_0" usage="cmd"> |
| <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> |
| </reg32> |
| - <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 --> |
| - <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd"> |
| + <!-- new in a6xx gen4, matches SP_CS_WGE_CNTL --> |
| + <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A6XX" usage="cmd"> |
| <!-- gl_LocalInvocationIndex --> |
| <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> |
| <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only |
| @@ -5102,7 +2961,18 @@ to upconvert to 32b float internally? |
| <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> |
| </reg32> |
| |
| - <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd"> |
| + <enum name="a7xx_workitem_rast_order"> |
| + <value value="0x0" name="WORKITEMRASTORDER_LINEAR"/> |
| + <doc> |
| + This is a fixed tiling, with 4x4 invocation outer tiles |
| + containing 2x2 invocation inner tiles. The intent is to |
| + improve cache locality with textures and images accessed |
| + using gl_LocalInvocationID. |
| + </doc> |
| + <value value="0x1" name="WORKITEMRASTORDER_TILED"/> |
| + </enum> |
| + |
| + <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A7XX-" usage="cmd"> |
| <!-- gl_LocalInvocationIndex --> |
| <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> |
| <!-- Must match SP_CS_CTRL --> |
| @@ -5110,18 +2980,16 @@ to upconvert to 32b float internally? |
| <!-- 1 thread per wave (would hang if THREAD128 is also set) --> |
| <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/> |
| |
| - <!-- Affects getone. If enabled, getone sometimes executed 1? less times |
| - than there are subgroups. |
| - --> |
| - <bitfield name="UNK15" pos="15" type="boolean"/> |
| + <doc>How invocations/fibers within a workgroup are tiled.</doc> |
| + <bitfield name="WORKITEMRASTORDER" pos="15" type="a7xx_workitem_rast_order"/> |
| </reg32> |
| |
| <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 --> |
| |
| - <reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/> |
| - <reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/> |
| - <reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/> |
| - <reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/> |
| + <reg64 offset="0xa9e0" name="SP_PS_SAMPLER_BASE" type="address" align="16" usage="rp_blit"/> |
| + <reg64 offset="0xa9e2" name="SP_CS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> |
| + <reg64 offset="0xa9e4" name="SP_PS_TEXMEMOBJ_BASE" type="address" align="64" usage="rp_blit"/> |
| + <reg64 offset="0xa9e6" name="SP_CS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> |
| |
| <enum name="a6xx_bindless_descriptor_size"> |
| <doc> |
| @@ -5146,18 +3014,19 @@ to upconvert to 32b float internally? |
| </array> |
| |
| <!-- |
| - IBO state for compute shader: |
| + UAV state for compute shader: |
| --> |
| - <reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/> |
| - <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/> |
| + <reg64 offset="0xa9f2" name="SP_CS_UAV_BASE" type="address" align="16" variants="A6XX"/> |
| + <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX"/> |
| + <reg32 offset="0xaa00" name="SP_CS_USIZE" low="0" high="6" type="uint"/> |
| |
| <!-- Correlated with avgs/uvgs usage in FS --> |
| - <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xaa01" name="SP_PS_VGS_CNTL" type="uint" variants="A7XX-" usage="cmd"/> |
| |
| - <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd"> |
| + <reg32 offset="0xaa02" name="SP_PS_OUTPUT_CONST_CNTL" variants="A7XX-" usage="cmd"> |
| <bitfield name="ENABLED" pos="0" type="boolean"/> |
| </reg32> |
| - <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd"> |
| + <reg32 offset="0xaa03" name="SP_PS_OUTPUT_CONST_MASK" variants="A7XX-" usage="cmd"> |
| <doc> |
| Specify for which components the output color should be read |
| from alias, e.g. for: |
| @@ -5167,7 +3036,7 @@ to upconvert to 32b float internally? |
| alias.1.b32.0 r1.x, c4.x |
| alias.1.b32.0 r0.x, c0.x |
| |
| - the SP_PS_ALIASED_COMPONENTS would be 0x00001111 |
| + the SP_PS_OUTPUT_CONST_MASK would be 0x00001111 |
| </doc> |
| |
| <bitfield name="RT0" low="0" high="3"/> |
| @@ -5193,7 +3062,7 @@ to upconvert to 32b float internally? |
| <value value="0x2" name="ISAMMODE_GL"/> |
| </enum> |
| |
| - <reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit"> |
| + <reg32 offset="0xab00" name="SP_MODE_CNTL" usage="rp_blit"> |
| <!-- |
| When set, half register loads from the constant file will |
| load a 32-bit value (so hc0.y loads the same value as c0.y) |
| @@ -5210,16 +3079,16 @@ to upconvert to 32b float internally? |
| <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/> |
| <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/> |
| |
| - <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> |
| - <reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> |
| + <reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> |
| + <reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> |
| |
| - <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> |
| + <array offset="0xab10" name="SP_GFX_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> |
| <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> |
| <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> |
| <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> |
| </reg64> |
| </array> |
| - <array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit"> |
| + <array offset="0xab0a" name="SP_GFX_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit"> |
| <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> |
| <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> |
| <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> |
| @@ -5227,15 +3096,15 @@ to upconvert to 32b float internally? |
| </array> |
| |
| <!-- |
| - Combined IBO state for 3d pipe, used for Image and SSBO write/atomic |
| - instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders. |
| + Combined UAV state for 3d pipe, used for Image and SSBO write/atomic |
| + instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. |
| --> |
| - <reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/> |
| - <reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/> |
| + <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> |
| + <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" usage="cmd"/> |
| |
| <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/> |
| |
| - <bitset name="a6xx_sp_2d_dst_format" inline="yes"> |
| + <bitset name="a6xx_sp_a2d_output_info" inline="yes"> |
| <bitfield name="NORM" pos="0" type="boolean"/> |
| <bitfield name="SINT" pos="1" type="boolean"/> |
| <bitfield name="UINT" pos="2" type="boolean"/> |
| @@ -5248,8 +3117,8 @@ to upconvert to 32b float internally? |
| <bitfield name="MASK" low="12" high="15"/> |
| </bitset> |
| |
| - <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xacc0" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xa9bf" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A7XX-" usage="rp_blit"/> |
| |
| <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/> |
| <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> |
| @@ -5257,16 +3126,16 @@ to upconvert to 32b float internally? |
| <!-- TODO: valid bits 0x3c3f, see kernel --> |
| </reg32> |
| <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/> |
| - <reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd"> |
| + <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="cmd"> |
| <bitfield name="F16_NO_INF" pos="3" type="boolean"/> |
| </reg32> |
| |
| <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/> |
| - <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/> |
| - <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/> |
| - <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="cmd"/> |
| |
| - <reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd"> |
| + <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="cmd"> |
| <!-- some perfcntrs are affected by a per-stage enable bit |
| (PERF_SP_ALU_WORKING_CYCLES for example) |
| TODO: verify position of HS/DS/GS bits --> |
| @@ -5281,7 +3150,7 @@ to upconvert to 32b float internally? |
| <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/> |
| <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/> |
| <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/> |
| - <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> |
| <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> |
| <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/> |
| <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/> |
| @@ -5301,33 +3170,44 @@ to upconvert to 32b float internally? |
| "a6xx_sp_ps_tp_cluster" but this actually specifies the border |
| color base for compute shaders. |
| --> |
| - <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/> |
| + <reg64 offset="0xb180" name="TPL1_CS_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> |
| <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/> |
| <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/> |
| |
| <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> |
| <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> |
| |
| - <!-- could be all the stuff below here is actually TPL1?? --> |
| - |
| - <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit"> |
| + <reg32 offset="0xb300" name="TPL1_RAS_MSAA_CNTL" usage="rp_blit"> |
| <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> |
| <bitfield name="UNK2" low="2" high="3"/> |
| </reg32> |
| - <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit"> |
| + <reg32 offset="0xb301" name="TPL1_DEST_MSAA_CNTL" usage="rp_blit"> |
| <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> |
| <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> |
| </reg32> |
| |
| <!-- looks to work in the same way as a5xx: --> |
| - <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/> |
| - <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> |
| - <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> |
| - <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> |
| - <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> |
| - <reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd"> |
| + <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> |
| + <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> |
| + <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> |
| + <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> |
| + <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> |
| + |
| + <enum name="a6xx_coord_round"> |
| + <value value="0" name="COORD_TRUNCATE"/> |
| + <value value="1" name="COORD_ROUND_NEAREST_EVEN"/> |
| + </enum> |
| + |
| + <enum name="a6xx_nearest_mode"> |
| + <value value="0" name="ROUND_CLAMP_TRUNCATE"/> |
| + <value value="1" name="CLAMP_ROUND_TRUNCATE"/> |
| + </enum> |
| + |
| + <reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd"> |
| <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> |
| - <bitfield name="UNK3" low="2" high="7"/> |
| + <bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/> |
| + <bitfield name="NEARESTMIPSNAP" pos="5" type="a6xx_nearest_mode"/> |
| + <bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/> |
| </reg32> |
| <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/> |
| |
| @@ -5336,42 +3216,45 @@ to upconvert to 32b float internally? |
| badly named or the functionality moved in a6xx. But downstream kernel |
| calls this "a6xx_sp_ps_tp_2d_cluster" |
| --> |
| - <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb4c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb4c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A6XX" usage="rp_blit"> |
| <bitfield name="WIDTH" low="0" high="14" type="uint"/> |
| <bitfield name="HEIGHT" low="15" high="29" type="uint"/> |
| </reg32> |
| - <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit"> |
| + <reg64 offset="0xb4c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb4c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A6XX" usage="rp_blit"> |
| <bitfield name="UNK0" low="0" high="8"/> |
| <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> |
| </reg32> |
| |
| - <reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX"> |
| + <reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX"> |
| <bitfield name="WIDTH" low="0" high="14" type="uint"/> |
| <bitfield name="HEIGHT" low="15" high="29" type="uint"/> |
| </reg32> |
| - <reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX"> |
| - <bitfield name="UNK0" low="0" high="8"/> |
| - <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> |
| + <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX"> |
| + <!-- |
| + Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE' |
| + is A6XX_TEX_IMG_BUFFER, which allows for lower alignment. |
| + --> |
| + <bitfield name="PITCH" low="3" high="23" type="uint"/> |
| </reg32> |
| |
| <!-- planes for NV12, etc. (TODO: not tested) --> |
| - <reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/> |
| - <reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A6XX"/> |
| - <reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/> |
| + <reg64 offset="0xb4c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A6XX"/> |
| + <reg32 offset="0xb4c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A6XX"/> |
| + <reg64 offset="0xb4c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A6XX"/> |
| |
| - <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/> |
| - <reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/> |
| - <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/> |
| + <reg64 offset="0xb2c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A7XX-"/> |
| + <reg32 offset="0xb2c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A7XX-"/> |
| + <reg64 offset="0xb2c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A7XX-"/> |
| |
| - <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/> |
| + <reg64 offset="0xb4ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb4cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/> |
| |
| - <reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/> |
| + <reg64 offset="0xb2ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xb2cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/> |
| |
| <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/> |
| <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/> |
| @@ -5383,8 +3266,12 @@ to upconvert to 32b float internally? |
| <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/> |
| <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/> |
| <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/> |
| - <reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> |
| - <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> |
| + <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="RAW_COPY" pos="0" type="boolean"/> |
| + <bitfield name="START_OFFSET_TEXELS" low="16" high="21"/> |
| + <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> |
| + </reg32> |
| <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/> |
| |
| <!-- always 0x100000 or 0x1000000? --> |
| @@ -5422,34 +3309,44 @@ to upconvert to 32b float internally? |
| |
| <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> |
| |
| - <bitset name="a6xx_hlsq_xs_cntl" inline="yes"> |
| + <bitset name="a6xx_xs_const_config" inline="yes"> |
| <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> |
| <bitfield name="ENABLED" pos="8" type="boolean"/> |
| <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/> |
| </bitset> |
| |
| - <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb800" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb801" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb802" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb803" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> |
| |
| - <reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa827" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa83f" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa867" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa898" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> |
| |
| - <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit"> |
| - <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG --> |
| - <bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/> |
| + <reg32 offset="0xa9aa" name="SP_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="FS_DISABLE" pos="0" type="boolean"/> |
| </reg32> |
| |
| - <!-- Always 0 --> |
| - <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa9ac" name="SP_DITHER_CNTL" variants="A7XX-" usage="cmd"> |
| + <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> |
| + <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> |
| + <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> |
| + <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> |
| + <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> |
| + <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> |
| + <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> |
| + <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> |
| + </reg32> |
| |
| - <!-- Used in VK_KHR_fragment_shading_rate --> |
| - <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa9ad" name="SP_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> |
| + <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> |
| + <bitfield name="ATTACHMENT_FSR_ENABLE" pos="1" type="boolean"/> |
| + <bitfield name="PRIMITIVE_FSR_ENABLE" pos="3" type="boolean"/> |
| + </reg32> |
| |
| - <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9ae" name="SP_PS_CNTL_1" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/> |
| <!-- UNK8 is set on a730/a740 --> |
| <bitfield name="UNK8" pos="8" type="boolean"/> |
| @@ -5462,94 +3359,94 @@ to upconvert to 32b float internally? |
| <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/> |
| |
| |
| - <bitset name="a6xx_hlsq_fs_cntl_0" inline="yes"> |
| + <bitset name="a6xx_sp_ps_wave_cntl" inline="yes"> |
| <!-- must match SP_FS_CTRL --> |
| <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/> |
| <bitfield name="VARYINGS" pos="1" type="boolean"/> |
| <bitfield name="UNK2" low="2" high="11"/> |
| </bitset> |
| - <bitset name="a6xx_hlsq_control_3_reg" inline="yes"> |
| + <bitset name="a6xx_sp_reg_prog_id_1" inline="yes"> |
| <!-- register loaded with position (bary.f) --> |
| <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/> |
| </bitset> |
| - <bitset name="a6xx_hlsq_control_4_reg" inline="yes"> |
| + <bitset name="a6xx_sp_reg_prog_id_2" inline="yes"> |
| <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> |
| </bitset> |
| - <bitset name="a6xx_hlsq_control_5_reg" inline="yes"> |
| + <bitset name="a6xx_sp_reg_prog_id_3" inline="yes"> |
| <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/> |
| <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/> |
| </bitset> |
| |
| - <reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb980" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A6XX" usage="rp_blit"/> |
| <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob --> |
| - <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb982" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A6XX" usage="rp_blit"> |
| <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the |
| A3xx field, except that it's not necessary to set it to anything but the maximum, since |
| the hardware will simply emit smaller waves when it runs out of space. --> |
| <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb983" name="SP_REG_PROG_ID_0" variants="A6XX" usage="rp_blit"> |
| <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> |
| <!-- SAMPLEID is loaded into a half-precision register: --> |
| <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/> |
| - <reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xb984" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb985" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb986" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb987" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="cmd"/> |
| + <reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa9c7" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9c8" name="SP_REG_PROG_ID_0" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> |
| <!-- SAMPLEID is loaded into a half-precision register: --> |
| <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> |
| <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/> |
| + <reg32 offset="0xa9c9" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa9ca" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa9cb" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa9cd" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="cmd"/> |
| |
| <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> |
| - <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb990" name="SP_CS_NDRANGE_0" variants="A6XX" usage="rp_blit"> |
| <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> |
| <!-- localsize is value minus one: --> |
| <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> |
| <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> |
| <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb991" name="SP_CS_NDRANGE_1" variants="A6XX" usage="rp_blit"> |
| <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb992" name="SP_CS_NDRANGE_2" variants="A6XX" usage="rp_blit"> |
| <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb993" name="SP_CS_NDRANGE_3" variants="A6XX" usage="rp_blit"> |
| <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb994" name="SP_CS_NDRANGE_4" variants="A6XX" usage="rp_blit"> |
| <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb995" name="SP_CS_NDRANGE_5" variants="A6XX" usage="rp_blit"> |
| <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb996" name="SP_CS_NDRANGE_6" variants="A6XX" usage="rp_blit"> |
| <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb997" name="SP_CS_CONST_CONFIG_0" variants="A6XX" usage="rp_blit"> |
| <!-- these are all vec3. first 3 need to be high regs |
| - WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0) |
| + WGSIZECONSTID is the local size (from SP_CS_NDRANGE_0) |
| WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID |
| --> |
| <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> |
| @@ -5557,7 +3454,7 @@ to upconvert to 32b float internally? |
| <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> |
| <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> |
| </reg32> |
| - <reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit"> |
| + <reg32 offset="0xb998" name="SP_CS_WGE_CNTL" variants="A6XX" usage="rp_blit"> |
| <!-- gl_LocalInvocationIndex --> |
| <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> |
| <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only |
| @@ -5569,40 +3466,40 @@ to upconvert to 32b float internally? |
| <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> |
| </reg32> |
| <!--note: vulkan blob doesn't use these --> |
| - <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb999" name="SP_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb99a" name="SP_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xb99b" name="SP_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/> |
| |
| <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> |
| - <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9d4" name="SP_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> |
| <!-- localsize is value minus one: --> |
| <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> |
| <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> |
| <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9d5" name="SP_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9d6" name="SP_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9d7" name="SP_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9d8" name="SP_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9d9" name="SP_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> |
| </reg32> |
| - <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9da" name="SP_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit"> |
| <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> |
| </reg32> |
| <!--note: vulkan blob doesn't use these --> |
| - <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/> |
| - <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa9dc" name="SP_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa9dd" name="SP_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xa9de" name="SP_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/> |
| |
| <enum name="a7xx_cs_yalign"> |
| <value name="CS_YALIGN_1" value="8"/> |
| @@ -5611,19 +3508,29 @@ to upconvert to 32b float internally? |
| <value name="CS_YALIGN_8" value="1"/> |
| </enum> |
| |
| - <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit"> |
| + <reg32 offset="0xa9db" name="SP_CS_WGE_CNTL" variants="A7XX-" usage="rp_blit"> |
| <!-- gl_LocalInvocationIndex --> |
| <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> |
| <!-- Must match SP_CS_CTRL --> |
| <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> |
| - <bitfield name="UNK11" pos="11" type="boolean"/> |
| - <bitfield name="UNK22" pos="22" type="boolean"/> |
| - <bitfield name="UNK26" pos="26" type="boolean"/> |
| - <bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/> |
| + <doc> |
| + When this bit is enabled, the dispatch order interleaves |
| + the z coordinate instead of launching all workgroups |
| + with z=0, then all with z=1 and so on. |
| + </doc> |
| + <bitfield name="WORKGROUPRASTORDERZFIRSTEN" pos="11" type="boolean"/> |
| + <doc> |
| + When both fields are non-0 then the dispatcher uses |
| + these tile sizes to launch workgroups in a tiled manner |
| + when the x and y workgroup counts are |
| + both more than 1. |
| + </doc> |
| + <bitfield name="WGTILEWIDTH" low="20" high="25"/> |
| + <bitfield name="WGTILEHEIGHT" low="26" high="31"/> |
| </reg32> |
| |
| - <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd"> |
| - <!-- localsize is value minus one: --> |
| + <reg32 offset="0xa9df" name="SP_CS_NDRANGE_7" variants="A7XX-" usage="cmd"> |
| + <!-- The size of the last workgroup. localsize is value minus one: --> |
| <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> |
| <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> |
| <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> |
| @@ -5641,29 +3548,27 @@ to upconvert to 32b float internally? |
| </reg64> |
| </array> |
| |
| - <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? --> |
| - <reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd"> |
| + <!-- new in a6xx gen4, mirror of SP_CS_CNTL_1? --> |
| + <reg32 offset="0xb9d0" name="HLSQ_CS_CTRL_REG1" variants="A6XX" usage="cmd"> |
| <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/> |
| - <bitfield name="UNK5" pos="5" type="boolean"/> |
| - <!-- always 1 ? --> |
| - <bitfield name="UNK6" pos="6" type="boolean"/> |
| + <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"/> |
| </reg32> |
| |
| - <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD" variants="A6XX"> |
| + <reg32 offset="0xbb00" name="SP_DRAW_INITIATOR" variants="A6XX"> |
| <bitfield name="STATE_ID" low="0" high="7"/> |
| </reg32> |
| |
| - <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD" variants="A6XX"> |
| + <reg32 offset="0xbb01" name="SP_KERNEL_INITIATOR" variants="A6XX"> |
| <bitfield name="STATE_ID" low="0" high="7"/> |
| </reg32> |
| |
| - <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD" variants="A6XX"> |
| + <reg32 offset="0xbb02" name="SP_EVENT_INITIATOR" variants="A6XX"> |
| <!-- I think only the low bit is actually used? --> |
| <bitfield name="STATE_ID" low="16" high="23"/> |
| <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> |
| </reg32> |
| |
| - <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd"> |
| + <reg32 offset="0xbb08" name="SP_UPDATE_CNTL" variants="A6XX" usage="cmd"> |
| <doc> |
| This register clears pending loads queued up by |
| CP_LOAD_STATE6. Each bit resets a particular kind(s) of |
| @@ -5678,8 +3583,8 @@ to upconvert to 32b float internally? |
| <bitfield name="FS_STATE" pos="4" type="boolean"/> |
| <bitfield name="CS_STATE" pos="5" type="boolean"/> |
| |
| - <bitfield name="CS_IBO" pos="6" type="boolean"/> |
| - <bitfield name="GFX_IBO" pos="7" type="boolean"/> |
| + <bitfield name="CS_UAV" pos="6" type="boolean"/> |
| + <bitfield name="GFX_UAV" pos="7" type="boolean"/> |
| |
| <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 --> |
| <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/> |
| @@ -5690,20 +3595,20 @@ to upconvert to 32b float internally? |
| <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/> |
| </reg32> |
| |
| - <reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-"> |
| + <reg32 offset="0xab1c" name="SP_DRAW_INITIATOR" variants="A7XX-"> |
| <bitfield name="STATE_ID" low="0" high="7"/> |
| </reg32> |
| |
| - <reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-"> |
| + <reg32 offset="0xab1d" name="SP_KERNEL_INITIATOR" variants="A7XX-"> |
| <bitfield name="STATE_ID" low="0" high="7"/> |
| </reg32> |
| |
| - <reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-"> |
| + <reg32 offset="0xab1e" name="SP_EVENT_INITIATOR" variants="A7XX-"> |
| <bitfield name="STATE_ID" low="16" high="23"/> |
| <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> |
| </reg32> |
| |
| - <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd"> |
| + <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX-" usage="cmd"> |
| <doc> |
| This register clears pending loads queued up by |
| CP_LOAD_STATE6. Each bit resets a particular kind(s) of |
| @@ -5718,18 +3623,18 @@ to upconvert to 32b float internally? |
| <bitfield name="FS_STATE" pos="4" type="boolean"/> |
| <bitfield name="CS_STATE" pos="5" type="boolean"/> |
| |
| - <bitfield name="CS_IBO" pos="6" type="boolean"/> |
| - <bitfield name="GFX_IBO" pos="7" type="boolean"/> |
| + <bitfield name="CS_UAV" pos="6" type="boolean"/> |
| + <bitfield name="GFX_UAV" pos="7" type="boolean"/> |
| |
| <!-- SS6_BINDLESS: one bit per bindless base --> |
| <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/> |
| <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/> |
| </reg32> |
| |
| - <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> |
| - <reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> |
| + <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> |
| + <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> |
| |
| - <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/> |
| + <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX_0" stride="1" length="64" variants="A7XX-"/> |
| |
| <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> |
| <doc> |
| @@ -5738,7 +3643,7 @@ to upconvert to 32b float internally? |
| const pool and 16 in the geometry const pool although |
| only 8 are actually used (why?) and they are mapped to |
| c504-c511 in each stage. Both VS and FS shared consts |
| - are written using ST6_CONSTANTS/SB6_IBO, so that both |
| + are written using ST6_CONSTANTS/SB6_UAV, so that both |
| the geometry and FS shared consts can be written at once |
| by using CP_LOAD_STATE6 rather than |
| CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition |
| @@ -5747,13 +3652,13 @@ to upconvert to 32b float internally? |
| |
| There is also a separate shared constant pool for CS, |
| which is loaded through CP_LOAD_STATE6_FRAG with |
| - ST6_UBO/ST6_IBO. However the only real difference for CS |
| + ST6_UBO/ST6_UAV. However the only real difference for CS |
| is the dword units. |
| </doc> |
| <bitfield name="ENABLE" pos="0" type="boolean"/> |
| </reg32> |
| |
| - <!-- mirror of SP_BINDLESS_BASE --> |
| + <!-- mirror of SP_GFX_BINDLESS_BASE --> |
| <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> |
| <reg64 offset="0" name="DESCRIPTOR"> |
| <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> |
| @@ -5788,10 +3693,10 @@ to upconvert to 32b float internally? |
| sequence. The sequence used internally for an event looks like: |
| - write EVENT_CMD pipe register |
| - write CP_EVENT_START |
| - - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD |
| - - write PC_EVENT_CMD with event or PC_DRAW_CMD |
| - - write HLSQ_EVENT_CMD(CONTEXT_DONE) |
| - - write PC_EVENT_CMD(CONTEXT_DONE) |
| + - write SP_EVENT_INITIATOR with event or SP_DRAW_INITIATOR |
| + - write PC_EVENT_INITIATOR with event or PC_DRAW_INITIATOR |
| + - write SP_EVENT_INITIATOR(CONTEXT_DONE) |
| + - write PC_EVENT_INITIATOR(CONTEXT_DONE) |
| - write CP_EVENT_END |
| Writing to CP_EVENT_END seems to actually trigger the context roll |
| --> |
| @@ -5809,193 +3714,6 @@ to upconvert to 32b float internally? |
| </reg32> |
| </domain> |
| |
| -<!-- Seems basically the same as a5xx, maybe move to common.xml.. --> |
| -<domain name="A6XX_TEX_SAMP" width="32"> |
| - <doc>Texture sampler dwords</doc> |
| - <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> |
| - <value name="A6XX_TEX_NEAREST" value="0"/> |
| - <value name="A6XX_TEX_LINEAR" value="1"/> |
| - <value name="A6XX_TEX_ANISO" value="2"/> |
| - <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> |
| - </enum> |
| - <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> |
| - <value name="A6XX_TEX_REPEAT" value="0"/> |
| - <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> |
| - <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> |
| - <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> |
| - <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> |
| - </enum> |
| - <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> |
| - <value name="A6XX_TEX_ANISO_1" value="0"/> |
| - <value name="A6XX_TEX_ANISO_2" value="1"/> |
| - <value name="A6XX_TEX_ANISO_4" value="2"/> |
| - <value name="A6XX_TEX_ANISO_8" value="3"/> |
| - <value name="A6XX_TEX_ANISO_16" value="4"/> |
| - </enum> |
| - <enum name="a6xx_reduction_mode"> |
| - <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> |
| - <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> |
| - <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> |
| - </enum> |
| - |
| - <reg32 offset="0" name="0"> |
| - <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> |
| - <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/> |
| - <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/> |
| - <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/> |
| - <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/> |
| - <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/> |
| - <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/> |
| - <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> |
| - </reg32> |
| - <reg32 offset="1" name="1"> |
| - <bitfield name="CLAMPENABLE" pos="0" type="boolean"> |
| - <doc> |
| - clamp result to [0, 1] if the format is unorm or |
| - [-1, 1] if the format is snorm, *after* |
| - filtering. Has no effect for other formats. |
| - </doc> |
| - </bitfield> |
| - <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> |
| - <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> |
| - <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> |
| - <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> |
| - <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> |
| - <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> |
| - </reg32> |
| - <reg32 offset="2" name="2"> |
| - <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/> |
| - <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/> |
| - <bitfield name="BCOLOR" low="7" high="31"/> |
| - </reg32> |
| - <reg32 offset="3" name="3"/> |
| -</domain> |
| - |
| -<domain name="A6XX_TEX_CONST" width="32" varset="chip"> |
| - <doc>Texture constant dwords</doc> |
| - <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> |
| - <value name="A6XX_TEX_X" value="0"/> |
| - <value name="A6XX_TEX_Y" value="1"/> |
| - <value name="A6XX_TEX_Z" value="2"/> |
| - <value name="A6XX_TEX_W" value="3"/> |
| - <value name="A6XX_TEX_ZERO" value="4"/> |
| - <value name="A6XX_TEX_ONE" value="5"/> |
| - </enum> |
| - <enum name="a6xx_tex_type"> <!-- same as a4xx? --> |
| - <value name="A6XX_TEX_1D" value="0"/> |
| - <value name="A6XX_TEX_2D" value="1"/> |
| - <value name="A6XX_TEX_CUBE" value="2"/> |
| - <value name="A6XX_TEX_3D" value="3"/> |
| - <value name="A6XX_TEX_BUFFER" value="4"/> |
| - </enum> |
| - <reg32 offset="0" name="0"> |
| - <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> |
| - <bitfield name="SRGB" pos="2" type="boolean"/> |
| - <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/> |
| - <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/> |
| - <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/> |
| - <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/> |
| - <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> |
| - <!-- overlaps with MIPLVLS --> |
| - <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/> |
| - <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/> |
| - <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> |
| - <bitfield name="FMT" low="22" high="29" type="a6xx_format"/> |
| - <!-- |
| - Why is the swap needed in addition to SWIZ_*? The swap |
| - is performed before border color replacement, while the |
| - swizzle is applied after after it. |
| - --> |
| - <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> |
| - </reg32> |
| - <reg32 offset="1" name="1"> |
| - <bitfield name="WIDTH" low="0" high="14" type="uint"/> |
| - <bitfield name="HEIGHT" low="15" high="29" type="uint"/> |
| - <bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/> |
| - </reg32> |
| - <reg32 offset="2" name="2"> |
| - <!-- |
| - These fields overlap PITCH, and are used instead of |
| - PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER. |
| - --> |
| - <doc> probably for D3D structured UAVs, normally set to 1 </doc> |
| - <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/> |
| - <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/> |
| - |
| - <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) --> |
| - <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/> |
| - <doc>Pitch in bytes (so actually stride)</doc> |
| - <bitfield name="PITCH" low="7" high="28" type="uint"/> |
| - <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> |
| - </reg32> |
| - <reg32 offset="3" name="3"> |
| - <!-- |
| - ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and |
| - for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the |
| - layer size at the point that it stops being reduced moving to |
| - higher (smaller) mipmap levels |
| - --> |
| - <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/> |
| - <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> |
| - <!-- |
| - by default levels with w < 16 are linear |
| - TILE_ALL makes all levels have tiling |
| - seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) |
| - --> |
| - <bitfield name="TILE_ALL" pos="27" type="boolean"/> |
| - <bitfield name="FLAG" pos="28" type="boolean"/> |
| - </reg32> |
| - <!-- for 2-3 plane format, BASE is flag buffer address (if enabled) |
| - the address of the non-flag base buffer is determined automatically, |
| - and must follow the flag buffer |
| - --> |
| - <reg32 offset="4" name="4"> |
| - <bitfield name="BASE_LO" low="5" high="31" shr="5"/> |
| - </reg32> |
| - <reg32 offset="5" name="5"> |
| - <bitfield name="BASE_HI" low="0" high="16"/> |
| - <bitfield name="DEPTH" low="17" high="29" type="uint"/> |
| - </reg32> |
| - <reg32 offset="6" name="6"> |
| - <!-- overlaps with PLANE_PITCH --> |
| - <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/> |
| - <!-- pitch for plane 2 / plane 3 --> |
| - <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/> |
| - </reg32> |
| - <!-- 7/8 is plane 2 address for planar formats --> |
| - <reg32 offset="7" name="7"> |
| - <bitfield name="FLAG_LO" low="5" high="31" shr="5"/> |
| - </reg32> |
| - <reg32 offset="8" name="8"> |
| - <bitfield name="FLAG_HI" low="0" high="16"/> |
| - </reg32> |
| - <!-- 9/10 is plane 3 address for planar formats --> |
| - <reg32 offset="9" name="9"> |
| - <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> |
| - </reg32> |
| - <reg32 offset="10" name="10"> |
| - <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> |
| - <!-- log2 size of the first level, required for mipmapping --> |
| - <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> |
| - <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> |
| - </reg32> |
| - <reg32 offset="11" name="11"/> |
| - <reg32 offset="12" name="12"/> |
| - <reg32 offset="13" name="13"/> |
| - <reg32 offset="14" name="14"/> |
| - <reg32 offset="15" name="15"/> |
| -</domain> |
| - |
| -<domain name="A6XX_UBO" width="32"> |
| - <reg32 offset="0" name="0"> |
| - <bitfield name="BASE_LO" low="0" high="31"/> |
| - </reg32> |
| - <reg32 offset="1" name="1"> |
| - <bitfield name="BASE_HI" low="0" high="16"/> |
| - <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units --> |
| - </reg32> |
| -</domain> |
| - |
| <domain name="A6XX_PDC" width="32"> |
| <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> |
| <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> |
| diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml |
| new file mode 100644 |
| index 000000000000..307d43dda8a2 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml |
| @@ -0,0 +1,198 @@ |
| +<?xml version="1.0" encoding="UTF-8"?> |
| +<database xmlns="http://nouveau.freedesktop.org/" |
| +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
| +xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| +<import file="freedreno_copyright.xml"/> |
| +<import file="adreno/adreno_common.xml"/> |
| +<import file="adreno/adreno_pm4.xml"/> |
| +<import file="adreno/a6xx_enums.xml"/> |
| + |
| +<domain name="A6XX_TEX_SAMP" width="32"> |
| + <doc>Texture sampler dwords</doc> |
| + <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> |
| + <value name="A6XX_TEX_NEAREST" value="0"/> |
| + <value name="A6XX_TEX_LINEAR" value="1"/> |
| + <value name="A6XX_TEX_ANISO" value="2"/> |
| + <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> |
| + </enum> |
| + <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> |
| + <value name="A6XX_TEX_REPEAT" value="0"/> |
| + <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> |
| + <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> |
| + <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> |
| + <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> |
| + </enum> |
| + <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> |
| + <value name="A6XX_TEX_ANISO_1" value="0"/> |
| + <value name="A6XX_TEX_ANISO_2" value="1"/> |
| + <value name="A6XX_TEX_ANISO_4" value="2"/> |
| + <value name="A6XX_TEX_ANISO_8" value="3"/> |
| + <value name="A6XX_TEX_ANISO_16" value="4"/> |
| + </enum> |
| + <enum name="a6xx_reduction_mode"> |
| + <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> |
| + <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> |
| + <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> |
| + </enum> |
| + <enum name="a6xx_fast_border_color"> |
| + <!-- R B G A --> |
| + <value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/> |
| + <value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/> |
| + <value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/> |
| + <value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/> |
| + </enum> |
| + |
| + <reg32 offset="0" name="0"> |
| + <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> |
| + <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/> |
| + <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/> |
| + <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/> |
| + <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/> |
| + <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/> |
| + <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/> |
| + <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> |
| + </reg32> |
| + <reg32 offset="1" name="1"> |
| + <bitfield name="CLAMPENABLE" pos="0" type="boolean"> |
| + <doc> |
| + clamp result to [0, 1] if the format is unorm or |
| + [-1, 1] if the format is snorm, *after* |
| + filtering. Has no effect for other formats. |
| + </doc> |
| + </bitfield> |
| + <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> |
| + <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> |
| + <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> |
| + <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> |
| + <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> |
| + <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> |
| + </reg32> |
| + <reg32 offset="2" name="2"> |
| + <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/> |
| + <bitfield name="FASTBORDERCOLOR" low="2" high="3" type="a6xx_fast_border_color"/> |
| + <bitfield name="FASTBORDERCOLOREN" pos="4" type="boolean"/> |
| + <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/> |
| + <bitfield name="BCOLOR" low="7" high="31"/> |
| + </reg32> |
| + <reg32 offset="3" name="3"/> |
| +</domain> |
| + |
| +<domain name="A6XX_TEX_CONST" width="32" varset="chip"> |
| + <doc>Texture constant dwords</doc> |
| + <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> |
| + <value name="A6XX_TEX_X" value="0"/> |
| + <value name="A6XX_TEX_Y" value="1"/> |
| + <value name="A6XX_TEX_Z" value="2"/> |
| + <value name="A6XX_TEX_W" value="3"/> |
| + <value name="A6XX_TEX_ZERO" value="4"/> |
| + <value name="A6XX_TEX_ONE" value="5"/> |
| + </enum> |
| + <reg32 offset="0" name="0"> |
| + <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> |
| + <bitfield name="SRGB" pos="2" type="boolean"/> |
| + <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/> |
| + <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/> |
| + <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/> |
| + <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/> |
| + <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> |
| + <!-- overlaps with MIPLVLS --> |
| + <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/> |
| + <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/> |
| + <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> |
| + <bitfield name="FMT" low="22" high="29" type="a6xx_format"/> |
| + <!-- |
| + Why is the swap needed in addition to SWIZ_*? The swap |
| + is performed before border color replacement, while the |
| + swizzle is applied after after it. |
| + --> |
| + <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> |
| + </reg32> |
| + <reg32 offset="1" name="1"> |
| + <bitfield name="WIDTH" low="0" high="14" type="uint"/> |
| + <bitfield name="HEIGHT" low="15" high="29" type="uint"/> |
| + <bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/> |
| + </reg32> |
| + <reg32 offset="2" name="2"> |
| + <!-- |
| + These fields overlap PITCH, and are used instead of |
| + PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER. |
| + --> |
| + <doc> probably for D3D structured UAVs, normally set to 1 </doc> |
| + <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/> |
| + <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/> |
| + |
| + <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) --> |
| + <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/> |
| + <doc>Pitch in bytes (so actually stride)</doc> |
| + <bitfield name="PITCH" low="7" high="28" type="uint"/> |
| + <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> |
| + </reg32> |
| + <reg32 offset="3" name="3"> |
| + <!-- |
| + ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and |
| + for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the |
| + layer size at the point that it stops being reduced moving to |
| + higher (smaller) mipmap levels |
| + --> |
| + <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/> |
| + <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> |
| + <!-- |
| + by default levels with w < 16 are linear |
| + TILE_ALL makes all levels have tiling |
| + seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) |
| + --> |
| + <bitfield name="TILE_ALL" pos="27" type="boolean"/> |
| + <bitfield name="FLAG" pos="28" type="boolean"/> |
| + </reg32> |
| + <!-- for 2-3 plane format, BASE is flag buffer address (if enabled) |
| + the address of the non-flag base buffer is determined automatically, |
| + and must follow the flag buffer |
| + --> |
| + <reg32 offset="4" name="4"> |
| + <bitfield name="BASE_LO" low="5" high="31" shr="5"/> |
| + </reg32> |
| + <reg32 offset="5" name="5"> |
| + <bitfield name="BASE_HI" low="0" high="16"/> |
| + <bitfield name="DEPTH" low="17" high="29" type="uint"/> |
| + </reg32> |
| + <reg32 offset="6" name="6"> |
| + <!-- overlaps with PLANE_PITCH --> |
| + <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/> |
| + <!-- pitch for plane 2 / plane 3 --> |
| + <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/> |
| + </reg32> |
| + <!-- 7/8 is plane 2 address for planar formats --> |
| + <reg32 offset="7" name="7"> |
| + <bitfield name="FLAG_LO" low="5" high="31" shr="5"/> |
| + </reg32> |
| + <reg32 offset="8" name="8"> |
| + <bitfield name="FLAG_HI" low="0" high="16"/> |
| + </reg32> |
| + <!-- 9/10 is plane 3 address for planar formats --> |
| + <reg32 offset="9" name="9"> |
| + <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> |
| + </reg32> |
| + <reg32 offset="10" name="10"> |
| + <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> |
| + <!-- log2 size of the first level, required for mipmapping --> |
| + <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> |
| + <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> |
| + </reg32> |
| + <reg32 offset="11" name="11"/> |
| + <reg32 offset="12" name="12"/> |
| + <reg32 offset="13" name="13"/> |
| + <reg32 offset="14" name="14"/> |
| + <reg32 offset="15" name="15"/> |
| +</domain> |
| + |
| +<domain name="A6XX_UBO" width="32"> |
| + <reg32 offset="0" name="0"> |
| + <bitfield name="BASE_LO" low="0" high="31"/> |
| + </reg32> |
| + <reg32 offset="1" name="1"> |
| + <bitfield name="BASE_HI" low="0" high="16"/> |
| + <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units --> |
| + </reg32> |
| +</domain> |
| + |
| +</database> |
| diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml |
| new file mode 100644 |
| index 000000000000..665539b098c6 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml |
| @@ -0,0 +1,383 @@ |
| +<?xml version="1.0" encoding="UTF-8"?> |
| +<database xmlns="http://nouveau.freedesktop.org/" |
| +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
| +xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| +<import file="freedreno_copyright.xml"/> |
| +<import file="adreno/adreno_common.xml"/> |
| +<import file="adreno/adreno_pm4.xml"/> |
| + |
| +<enum name="a6xx_tile_mode"> |
| + <value name="TILE6_LINEAR" value="0"/> |
| + <value name="TILE6_2" value="2"/> |
| + <value name="TILE6_3" value="3"/> |
| +</enum> |
| + |
| +<enum name="a6xx_format"> |
| + <value value="0x02" name="FMT6_A8_UNORM"/> |
| + <value value="0x03" name="FMT6_8_UNORM"/> |
| + <value value="0x04" name="FMT6_8_SNORM"/> |
| + <value value="0x05" name="FMT6_8_UINT"/> |
| + <value value="0x06" name="FMT6_8_SINT"/> |
| + |
| + <value value="0x08" name="FMT6_4_4_4_4_UNORM"/> |
| + <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/> |
| + <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only --> |
| + <value value="0x0e" name="FMT6_5_6_5_UNORM"/> |
| + |
| + <value value="0x0f" name="FMT6_8_8_UNORM"/> |
| + <value value="0x10" name="FMT6_8_8_SNORM"/> |
| + <value value="0x11" name="FMT6_8_8_UINT"/> |
| + <value value="0x12" name="FMT6_8_8_SINT"/> |
| + <value value="0x13" name="FMT6_L8_A8_UNORM"/> |
| + |
| + <value value="0x15" name="FMT6_16_UNORM"/> |
| + <value value="0x16" name="FMT6_16_SNORM"/> |
| + <value value="0x17" name="FMT6_16_FLOAT"/> |
| + <value value="0x18" name="FMT6_16_UINT"/> |
| + <value value="0x19" name="FMT6_16_SINT"/> |
| + |
| + <value value="0x21" name="FMT6_8_8_8_UNORM"/> |
| + <value value="0x22" name="FMT6_8_8_8_SNORM"/> |
| + <value value="0x23" name="FMT6_8_8_8_UINT"/> |
| + <value value="0x24" name="FMT6_8_8_8_SINT"/> |
| + |
| + <value value="0x30" name="FMT6_8_8_8_8_UNORM"/> |
| + <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha --> |
| + <value value="0x32" name="FMT6_8_8_8_8_SNORM"/> |
| + <value value="0x33" name="FMT6_8_8_8_8_UINT"/> |
| + <value value="0x34" name="FMT6_8_8_8_8_SINT"/> |
| + |
| + <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/> |
| + |
| + <value value="0x36" name="FMT6_10_10_10_2_UNORM"/> |
| + <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/> |
| + <value value="0x39" name="FMT6_10_10_10_2_SNORM"/> |
| + <value value="0x3a" name="FMT6_10_10_10_2_UINT"/> |
| + <value value="0x3b" name="FMT6_10_10_10_2_SINT"/> |
| + |
| + <value value="0x42" name="FMT6_11_11_10_FLOAT"/> |
| + |
| + <value value="0x43" name="FMT6_16_16_UNORM"/> |
| + <value value="0x44" name="FMT6_16_16_SNORM"/> |
| + <value value="0x45" name="FMT6_16_16_FLOAT"/> |
| + <value value="0x46" name="FMT6_16_16_UINT"/> |
| + <value value="0x47" name="FMT6_16_16_SINT"/> |
| + |
| + <value value="0x48" name="FMT6_32_UNORM"/> |
| + <value value="0x49" name="FMT6_32_SNORM"/> |
| + <value value="0x4a" name="FMT6_32_FLOAT"/> |
| + <value value="0x4b" name="FMT6_32_UINT"/> |
| + <value value="0x4c" name="FMT6_32_SINT"/> |
| + <value value="0x4d" name="FMT6_32_FIXED"/> |
| + |
| + <value value="0x58" name="FMT6_16_16_16_UNORM"/> |
| + <value value="0x59" name="FMT6_16_16_16_SNORM"/> |
| + <value value="0x5a" name="FMT6_16_16_16_FLOAT"/> |
| + <value value="0x5b" name="FMT6_16_16_16_UINT"/> |
| + <value value="0x5c" name="FMT6_16_16_16_SINT"/> |
| + |
| + <value value="0x60" name="FMT6_16_16_16_16_UNORM"/> |
| + <value value="0x61" name="FMT6_16_16_16_16_SNORM"/> |
| + <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/> |
| + <value value="0x63" name="FMT6_16_16_16_16_UINT"/> |
| + <value value="0x64" name="FMT6_16_16_16_16_SINT"/> |
| + |
| + <value value="0x65" name="FMT6_32_32_UNORM"/> |
| + <value value="0x66" name="FMT6_32_32_SNORM"/> |
| + <value value="0x67" name="FMT6_32_32_FLOAT"/> |
| + <value value="0x68" name="FMT6_32_32_UINT"/> |
| + <value value="0x69" name="FMT6_32_32_SINT"/> |
| + <value value="0x6a" name="FMT6_32_32_FIXED"/> |
| + |
| + <value value="0x70" name="FMT6_32_32_32_UNORM"/> |
| + <value value="0x71" name="FMT6_32_32_32_SNORM"/> |
| + <value value="0x72" name="FMT6_32_32_32_UINT"/> |
| + <value value="0x73" name="FMT6_32_32_32_SINT"/> |
| + <value value="0x74" name="FMT6_32_32_32_FLOAT"/> |
| + <value value="0x75" name="FMT6_32_32_32_FIXED"/> |
| + |
| + <value value="0x80" name="FMT6_32_32_32_32_UNORM"/> |
| + <value value="0x81" name="FMT6_32_32_32_32_SNORM"/> |
| + <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/> |
| + <value value="0x83" name="FMT6_32_32_32_32_UINT"/> |
| + <value value="0x84" name="FMT6_32_32_32_32_SINT"/> |
| + <value value="0x85" name="FMT6_32_32_32_32_FIXED"/> |
| + |
| + <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY --> |
| + <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV --> |
| + <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 --> |
| + <value value="0x8f" name="FMT6_NV21"/> |
| + <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 --> |
| + |
| + <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/> |
| + |
| + <!-- Note: tiling/UBWC for these may be different from equivalent formats |
| + For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM |
| + --> |
| + <value value="0x94" name="FMT6_NV12_Y"/> |
| + <value value="0x95" name="FMT6_NV12_UV"/> |
| + <value value="0x96" name="FMT6_NV12_VU"/> |
| + <value value="0x97" name="FMT6_NV12_4R"/> |
| + <value value="0x98" name="FMT6_NV12_4R_Y"/> |
| + <value value="0x99" name="FMT6_NV12_4R_UV"/> |
| + <value value="0x9a" name="FMT6_P010"/> |
| + <value value="0x9b" name="FMT6_P010_Y"/> |
| + <value value="0x9c" name="FMT6_P010_UV"/> |
| + <value value="0x9d" name="FMT6_TP10"/> |
| + <value value="0x9e" name="FMT6_TP10_Y"/> |
| + <value value="0x9f" name="FMT6_TP10_UV"/> |
| + |
| + <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/> |
| + |
| + <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/> |
| + <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/> |
| + <value value="0xad" name="FMT6_ETC2_R11_UNORM"/> |
| + <value value="0xae" name="FMT6_ETC2_R11_SNORM"/> |
| + <value value="0xaf" name="FMT6_ETC1"/> |
| + <value value="0xb0" name="FMT6_ETC2_RGB8"/> |
| + <value value="0xb1" name="FMT6_ETC2_RGBA8"/> |
| + <value value="0xb2" name="FMT6_ETC2_RGB8A1"/> |
| + <value value="0xb3" name="FMT6_DXT1"/> |
| + <value value="0xb4" name="FMT6_DXT3"/> |
| + <value value="0xb5" name="FMT6_DXT5"/> |
| + <value value="0xb6" name="FMT6_RGTC1_UNORM"/> |
| + <value value="0xb7" name="FMT6_RGTC1_UNORM_FAST"/> |
| + <value value="0xb8" name="FMT6_RGTC1_SNORM"/> |
| + <value value="0xb9" name="FMT6_RGTC1_SNORM_FAST"/> |
| + <value value="0xba" name="FMT6_RGTC2_UNORM"/> |
| + <value value="0xbb" name="FMT6_RGTC2_UNORM_FAST"/> |
| + <value value="0xbc" name="FMT6_RGTC2_SNORM"/> |
| + <value value="0xbd" name="FMT6_RGTC2_SNORM_FAST"/> |
| + <value value="0xbe" name="FMT6_BPTC_UFLOAT"/> |
| + <value value="0xbf" name="FMT6_BPTC_FLOAT"/> |
| + <value value="0xc0" name="FMT6_BPTC"/> |
| + <value value="0xc1" name="FMT6_ASTC_4x4"/> |
| + <value value="0xc2" name="FMT6_ASTC_5x4"/> |
| + <value value="0xc3" name="FMT6_ASTC_5x5"/> |
| + <value value="0xc4" name="FMT6_ASTC_6x5"/> |
| + <value value="0xc5" name="FMT6_ASTC_6x6"/> |
| + <value value="0xc6" name="FMT6_ASTC_8x5"/> |
| + <value value="0xc7" name="FMT6_ASTC_8x6"/> |
| + <value value="0xc8" name="FMT6_ASTC_8x8"/> |
| + <value value="0xc9" name="FMT6_ASTC_10x5"/> |
| + <value value="0xca" name="FMT6_ASTC_10x6"/> |
| + <value value="0xcb" name="FMT6_ASTC_10x8"/> |
| + <value value="0xcc" name="FMT6_ASTC_10x10"/> |
| + <value value="0xcd" name="FMT6_ASTC_12x10"/> |
| + <value value="0xce" name="FMT6_ASTC_12x12"/> |
| + |
| + <!-- for sampling stencil (integer, 2nd channel), not available on a630 --> |
| + <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/> |
| + |
| + <!-- Not a hw enum, used internally in driver --> |
| + <value value="0xff" name="FMT6_NONE"/> |
| + |
| +</enum> |
| + |
| +<!-- probably same as a5xx --> |
| +<enum name="a6xx_polygon_mode"> |
| + <value name="POLYMODE6_POINTS" value="1"/> |
| + <value name="POLYMODE6_LINES" value="2"/> |
| + <value name="POLYMODE6_TRIANGLES" value="3"/> |
| +</enum> |
| + |
| +<enum name="a6xx_depth_format"> |
| + <value name="DEPTH6_NONE" value="0"/> |
| + <value name="DEPTH6_16" value="1"/> |
| + <value name="DEPTH6_24_8" value="2"/> |
| + <value name="DEPTH6_32" value="4"/> |
| +</enum> |
| + |
| +<bitset name="a6x_cp_protect" inline="yes"> |
| + <bitfield name="BASE_ADDR" low="0" high="17"/> |
| + <bitfield name="MASK_LEN" low="18" high="30"/> |
| + <bitfield name="READ" pos="31" type="boolean"/> |
| +</bitset> |
| + |
| +<enum name="a6xx_shader_id"> |
| + <value value="0x9" name="A6XX_TP0_TMO_DATA"/> |
| + <value value="0xa" name="A6XX_TP0_SMO_DATA"/> |
| + <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/> |
| + <value value="0x19" name="A6XX_TP1_TMO_DATA"/> |
| + <value value="0x1a" name="A6XX_TP1_SMO_DATA"/> |
| + <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/> |
| + <value value="0x29" name="A6XX_SP_INST_DATA"/> |
| + <value value="0x2a" name="A6XX_SP_LB_0_DATA"/> |
| + <value value="0x2b" name="A6XX_SP_LB_1_DATA"/> |
| + <value value="0x2c" name="A6XX_SP_LB_2_DATA"/> |
| + <value value="0x2d" name="A6XX_SP_LB_3_DATA"/> |
| + <value value="0x2e" name="A6XX_SP_LB_4_DATA"/> |
| + <value value="0x2f" name="A6XX_SP_LB_5_DATA"/> |
| + <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/> |
| + <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/> |
| + <value value="0x32" name="A6XX_SP_GFX_UAV_BASE_DATA"/> |
| + <value value="0x33" name="A6XX_SP_INST_TAG"/> |
| + <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/> |
| + <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/> |
| + <value value="0x36" name="A6XX_SP_SMO_TAG"/> |
| + <value value="0x37" name="A6XX_SP_STATE_DATA"/> |
| + <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/> |
| + <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/> |
| + <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/> |
| + <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/> |
| + <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> |
| + <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> |
| + <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/> |
| + <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/> |
| + <value value="0x52" name="A6XX_HLSQ_INST_RAM"/> |
| + <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/> |
| + <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/> |
| + <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/> |
| + <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/> |
| + <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/> |
| + <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> |
| + <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> |
| + <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/> |
| + <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/> |
| + <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/> |
| + <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/> |
| + <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/> |
| + <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/> |
| + <value value="0x70" name="A6XX_SP_LB_6_DATA"/> |
| + <value value="0x71" name="A6XX_SP_LB_7_DATA"/> |
| + <value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/> |
| +</enum> |
| + |
| +<enum name="a6xx_debugbus_id"> |
| + <value value="0x1" name="A6XX_DBGBUS_CP"/> |
| + <value value="0x2" name="A6XX_DBGBUS_RBBM"/> |
| + <value value="0x3" name="A6XX_DBGBUS_VBIF"/> |
| + <value value="0x4" name="A6XX_DBGBUS_HLSQ"/> |
| + <value value="0x5" name="A6XX_DBGBUS_UCHE"/> |
| + <value value="0x6" name="A6XX_DBGBUS_DPM"/> |
| + <value value="0x7" name="A6XX_DBGBUS_TESS"/> |
| + <value value="0x8" name="A6XX_DBGBUS_PC"/> |
| + <value value="0x9" name="A6XX_DBGBUS_VFDP"/> |
| + <value value="0xa" name="A6XX_DBGBUS_VPC"/> |
| + <value value="0xb" name="A6XX_DBGBUS_TSE"/> |
| + <value value="0xc" name="A6XX_DBGBUS_RAS"/> |
| + <value value="0xd" name="A6XX_DBGBUS_VSC"/> |
| + <value value="0xe" name="A6XX_DBGBUS_COM"/> |
| + <value value="0x10" name="A6XX_DBGBUS_LRZ"/> |
| + <value value="0x11" name="A6XX_DBGBUS_A2D"/> |
| + <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/> |
| + <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/> |
| + <value value="0x14" name="A6XX_DBGBUS_RBP"/> |
| + <value value="0x15" name="A6XX_DBGBUS_DCS"/> |
| + <value value="0x16" name="A6XX_DBGBUS_DBGC"/> |
| + <value value="0x17" name="A6XX_DBGBUS_CX"/> |
| + <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/> |
| + <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/> |
| + <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/> |
| + <value value="0x1d" name="A6XX_DBGBUS_GPC"/> |
| + <value value="0x1e" name="A6XX_DBGBUS_LARC"/> |
| + <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/> |
| + <value value="0x20" name="A6XX_DBGBUS_RB_0"/> |
| + <value value="0x21" name="A6XX_DBGBUS_RB_1"/> |
| + <value value="0x22" name="A6XX_DBGBUS_RB_2"/> |
| + <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/> |
| + <value value="0x28" name="A6XX_DBGBUS_CCU_0"/> |
| + <value value="0x29" name="A6XX_DBGBUS_CCU_1"/> |
| + <value value="0x2a" name="A6XX_DBGBUS_CCU_2"/> |
| + <value value="0x38" name="A6XX_DBGBUS_VFD_0"/> |
| + <value value="0x39" name="A6XX_DBGBUS_VFD_1"/> |
| + <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/> |
| + <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/> |
| + <value value="0x3c" name="A6XX_DBGBUS_VFD_4"/> |
| + <value value="0x3d" name="A6XX_DBGBUS_VFD_5"/> |
| + <value value="0x40" name="A6XX_DBGBUS_SP_0"/> |
| + <value value="0x41" name="A6XX_DBGBUS_SP_1"/> |
| + <value value="0x42" name="A6XX_DBGBUS_SP_2"/> |
| + <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/> |
| + <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/> |
| + <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/> |
| + <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/> |
| + <value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/> |
| + <value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/> |
| + <value value="0x58" name="A6XX_DBGBUS_SPTP_0"/> |
| + <value value="0x59" name="A6XX_DBGBUS_SPTP_1"/> |
| + <value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/> |
| + <value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/> |
| + <value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/> |
| + <value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/> |
| +</enum> |
| + |
| +<!-- |
| +Used in a6xx_a2d_bit_cntl.. the value mostly seems to correlate to the |
| +component type/size, so I think it relates to internal format used for |
| +blending? The one exception is that 16b unorm and 32b float use the |
| +same value... maybe 16b unorm is uncommon enough that it was just easier |
| +to upconvert to 32b float internally? |
| + |
| + 8b unorm: 10 (sometimes 0, is the high bit part of something else?) |
| +16b unorm: 4 |
| + |
| +32b int: 7 |
| +16b int: 6 |
| + 8b int: 5 |
| + |
| +32b float: 4 |
| +16b float: 3 |
| + --> |
| +<enum name="a6xx_2d_ifmt"> |
| + <value value="0x10" name="R2D_UNORM8"/> |
| + <value value="0x7" name="R2D_INT32"/> |
| + <value value="0x6" name="R2D_INT16"/> |
| + <value value="0x5" name="R2D_INT8"/> |
| + <value value="0x4" name="R2D_FLOAT32"/> |
| + <value value="0x3" name="R2D_FLOAT16"/> |
| + <value value="0x1" name="R2D_UNORM8_SRGB"/> |
| + <value value="0x0" name="R2D_RAW"/> |
| +</enum> |
| + |
| +<enum name="a6xx_tex_type"> |
| + <value name="A6XX_TEX_1D" value="0"/> |
| + <value name="A6XX_TEX_2D" value="1"/> |
| + <value name="A6XX_TEX_CUBE" value="2"/> |
| + <value name="A6XX_TEX_3D" value="3"/> |
| + <value name="A6XX_TEX_BUFFER" value="4"/> |
| + <doc> |
| + A special buffer type for usage as the source for buffer |
| + to image copies with lower alignment requirements than |
| + A6XX_TEX_2D, available since A7XX. |
| + </doc> |
| + <value name="A6XX_TEX_IMG_BUFFER" value="5"/> |
| +</enum> |
| + |
| +<enum name="a6xx_ztest_mode"> |
| + <doc>Allow early z-test and early-lrz (if applicable)</doc> |
| + <value value="0x0" name="A6XX_EARLY_Z"/> |
| + <doc>Disable early z-test and early-lrz test (if applicable)</doc> |
| + <value value="0x1" name="A6XX_LATE_Z"/> |
| + <doc> |
| + A special mode that allows early-lrz (if applicable) or early-z |
| + tests, but also does late-z tests at which point it writes depth. |
| + |
| + This mode is used when fragment can be killed (via discard or |
| + sample mask) after early-z tests and it writes depth. In such case |
| + depth can be written only at late-z stage, but it's ok to use |
| + early-z to discard fragments. |
| + |
| + However this mode is not compatible with: |
| + - Lack of D/S attachment |
| + - Stencil writes on stencil or depth test failures |
| + - Per-sample shading |
| + </doc> |
| + <value value="0x2" name="A6XX_EARLY_Z_LATE_Z"/> |
| + <doc>Not a real hw value, used internally by mesa</doc> |
| + <value value="0x3" name="A6XX_INVALID_ZTEST"/> |
| +</enum> |
| + |
| +<enum name="a6xx_tess_spacing"> |
| + <value value="0x0" name="TESS_EQUAL"/> |
| + <value value="0x2" name="TESS_FRACTIONAL_ODD"/> |
| + <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> |
| +</enum> |
| +<enum name="a6xx_tess_output"> |
| + <value value="0x0" name="TESS_POINTS"/> |
| + <value value="0x1" name="TESS_LINES"/> |
| + <value value="0x2" name="TESS_CW_TRIS"/> |
| + <value value="0x3" name="TESS_CCW_TRIS"/> |
| +</enum> |
| + |
| +</database> |
| diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.xml |
| new file mode 100644 |
| index 000000000000..c446a2eb1120 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.xml |
| @@ -0,0 +1,600 @@ |
| +<?xml version="1.0" encoding="UTF-8"?> |
| +<database xmlns="http://nouveau.freedesktop.org/" |
| +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
| +xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| +<import file="freedreno_copyright.xml"/> |
| +<import file="adreno/adreno_common.xml"/> |
| +<import file="adreno/adreno_pm4.xml"/> |
| + |
| +<enum name="a6xx_cp_perfcounter_select"> |
| + <value value="0" name="PERF_CP_ALWAYS_COUNT"/> |
| + <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> |
| + <value value="2" name="PERF_CP_BUSY_CYCLES"/> |
| + <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> |
| + <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> |
| + <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> |
| + <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> |
| + <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> |
| + <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> |
| + <value value="9" name="PERF_CP_MODE_SWITCH"/> |
| + <value value="10" name="PERF_CP_ZPASS_DONE"/> |
| + <value value="11" name="PERF_CP_CONTEXT_DONE"/> |
| + <value value="12" name="PERF_CP_CACHE_FLUSH"/> |
| + <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> |
| + <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> |
| + <value value="15" name="PERF_CP_SQE_IDLE"/> |
| + <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> |
| + <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> |
| + <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> |
| + <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> |
| + <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> |
| + <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> |
| + <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> |
| + <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> |
| + <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> |
| + <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> |
| + <value value="26" name="PERF_CP_SQE_T4_EXEC"/> |
| + <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> |
| + <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> |
| + <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> |
| + <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> |
| + <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> |
| + <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> |
| + <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> |
| + <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> |
| + <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> |
| + <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> |
| + <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> |
| + <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> |
| + <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> |
| + <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> |
| + <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> |
| + <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> |
| + <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> |
| + <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> |
| + <value value="45" name="PERF_CP_PM4_DATA"/> |
| + <value value="46" name="PERF_CP_PM4_HEADERS"/> |
| + <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> |
| + <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> |
| + <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> |
| +</enum> |
| + |
| +<enum name="a6xx_rbbm_perfcounter_select"> |
| + <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> |
| + <value value="1" name="PERF_RBBM_ALWAYS_ON"/> |
| + <value value="2" name="PERF_RBBM_TSE_BUSY"/> |
| + <value value="3" name="PERF_RBBM_RAS_BUSY"/> |
| + <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> |
| + <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> |
| + <value value="6" name="PERF_RBBM_STATUS_MASKED"/> |
| + <value value="7" name="PERF_RBBM_COM_BUSY"/> |
| + <value value="8" name="PERF_RBBM_DCOM_BUSY"/> |
| + <value value="9" name="PERF_RBBM_VBIF_BUSY"/> |
| + <value value="10" name="PERF_RBBM_VSC_BUSY"/> |
| + <value value="11" name="PERF_RBBM_TESS_BUSY"/> |
| + <value value="12" name="PERF_RBBM_UCHE_BUSY"/> |
| + <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> |
| +</enum> |
| + |
| +<enum name="a6xx_pc_perfcounter_select"> |
| + <value value="0" name="PERF_PC_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_PC_WORKING_CYCLES"/> |
| + <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> |
| + <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> |
| + <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> |
| + <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> |
| + <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> |
| + <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> |
| + <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> |
| + <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> |
| + <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> |
| + <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> |
| + <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> |
| + <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> |
| + <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> |
| + <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> |
| + <value value="16" name="PERF_PC_INSTANCES"/> |
| + <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> |
| + <value value="18" name="PERF_PC_DEAD_PRIM"/> |
| + <value value="19" name="PERF_PC_LIVE_PRIM"/> |
| + <value value="20" name="PERF_PC_VERTEX_HITS"/> |
| + <value value="21" name="PERF_PC_IA_VERTICES"/> |
| + <value value="22" name="PERF_PC_IA_PRIMITIVES"/> |
| + <value value="23" name="PERF_PC_GS_PRIMITIVES"/> |
| + <value value="24" name="PERF_PC_HS_INVOCATIONS"/> |
| + <value value="25" name="PERF_PC_DS_INVOCATIONS"/> |
| + <value value="26" name="PERF_PC_VS_INVOCATIONS"/> |
| + <value value="27" name="PERF_PC_GS_INVOCATIONS"/> |
| + <value value="28" name="PERF_PC_DS_PRIMITIVES"/> |
| + <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> |
| + <value value="30" name="PERF_PC_3D_DRAWCALLS"/> |
| + <value value="31" name="PERF_PC_2D_DRAWCALLS"/> |
| + <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> |
| + <value value="33" name="PERF_TESS_BUSY_CYCLES"/> |
| + <value value="34" name="PERF_TESS_WORKING_CYCLES"/> |
| + <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> |
| + <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> |
| + <value value="37" name="PERF_PC_TSE_TRANSACTION"/> |
| + <value value="38" name="PERF_PC_TSE_VERTEX"/> |
| + <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> |
| + <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> |
| + <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> |
| +</enum> |
| + |
| +<enum name="a6xx_vfd_perfcounter_select"> |
| + <value value="0" name="PERF_VFD_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> |
| + <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> |
| + <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> |
| + <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> |
| + <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> |
| + <value value="6" name="PERF_VFD_RBUFFER_FULL"/> |
| + <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> |
| + <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> |
| + <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> |
| + <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> |
| + <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> |
| + <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> |
| + <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> |
| + <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> |
| + <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> |
| + <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> |
| + <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> |
| + <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> |
| + <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> |
| + <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> |
| + <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> |
| + <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> |
| +</enum> |
| + |
| +<enum name="a6xx_hlsq_perfcounter_select"> |
| + <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> |
| + <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> |
| + <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> |
| + <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> |
| + <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> |
| + <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> |
| + <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> |
| + <value value="8" name="PERF_HLSQ_QUADS"/> |
| + <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> |
| + <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> |
| + <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> |
| + <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> |
| + <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> |
| + <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> |
| + <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> |
| + <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> |
| + <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> |
| + <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> |
| + <value value="19" name="PERF_HLSQ_PIXELS"/> |
| + <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> |
| +</enum> |
| + |
| +<enum name="a6xx_vpc_perfcounter_select"> |
| + <value value="0" name="PERF_VPC_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_VPC_WORKING_CYCLES"/> |
| + <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> |
| + <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> |
| + <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> |
| + <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> |
| + <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> |
| + <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> |
| + <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> |
| + <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> |
| + <value value="10" name="PERF_VPC_SP_COMPONENTS"/> |
| + <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> |
| + <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> |
| + <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> |
| + <value value="14" name="PERF_VPC_LM_TRANSACTION"/> |
| + <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> |
| + <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> |
| + <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> |
| + <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> |
| + <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> |
| + <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> |
| + <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> |
| + <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> |
| + <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> |
| + <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> |
| + <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> |
| + <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> |
| + <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> |
| +</enum> |
| + |
| +<enum name="a6xx_tse_perfcounter_select"> |
| + <value value="0" name="PERF_TSE_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> |
| + <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> |
| + <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> |
| + <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> |
| + <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> |
| + <value value="6" name="PERF_TSE_INPUT_PRIM"/> |
| + <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> |
| + <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> |
| + <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> |
| + <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> |
| + <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> |
| + <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> |
| + <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> |
| + <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> |
| + <value value="15" name="PERF_TSE_CINVOCATION"/> |
| + <value value="16" name="PERF_TSE_CPRIMITIVES"/> |
| + <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> |
| + <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> |
| + <value value="19" name="PERF_TSE_CLIP_PLANES"/> |
| +</enum> |
| + |
| +<enum name="a6xx_ras_perfcounter_select"> |
| + <value value="0" name="PERF_RAS_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> |
| + <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> |
| + <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> |
| + <value value="4" name="PERF_RAS_SUPER_TILES"/> |
| + <value value="5" name="PERF_RAS_8X4_TILES"/> |
| + <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> |
| + <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> |
| + <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> |
| + <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> |
| + <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> |
| + <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> |
| + <value value="12" name="PERF_RAS_BLOCKS"/> |
| +</enum> |
| + |
| +<enum name="a6xx_uche_perfcounter_select"> |
| + <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> |
| + <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> |
| + <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> |
| + <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> |
| + <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> |
| + <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> |
| + <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> |
| + <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> |
| + <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> |
| + <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> |
| + <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> |
| + <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> |
| + <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> |
| + <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> |
| + <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> |
| + <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> |
| + <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> |
| + <value value="18" name="PERF_UCHE_EVICTS"/> |
| + <value value="19" name="PERF_UCHE_BANK_REQ0"/> |
| + <value value="20" name="PERF_UCHE_BANK_REQ1"/> |
| + <value value="21" name="PERF_UCHE_BANK_REQ2"/> |
| + <value value="22" name="PERF_UCHE_BANK_REQ3"/> |
| + <value value="23" name="PERF_UCHE_BANK_REQ4"/> |
| + <value value="24" name="PERF_UCHE_BANK_REQ5"/> |
| + <value value="25" name="PERF_UCHE_BANK_REQ6"/> |
| + <value value="26" name="PERF_UCHE_BANK_REQ7"/> |
| + <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> |
| + <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> |
| + <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> |
| + <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> |
| + <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> |
| + <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> |
| + <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> |
| + <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> |
| + <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> |
| + <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> |
| + <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> |
| + <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> |
| + <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> |
| +</enum> |
| + |
| +<enum name="a6xx_tp_perfcounter_select"> |
| + <value value="0" name="PERF_TP_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> |
| + <value value="2" name="PERF_TP_LATENCY_CYCLES"/> |
| + <value value="3" name="PERF_TP_LATENCY_TRANS"/> |
| + <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> |
| + <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> |
| + <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> |
| + <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> |
| + <value value="8" name="PERF_TP_SP_TP_TRANS"/> |
| + <value value="9" name="PERF_TP_TP_SP_TRANS"/> |
| + <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> |
| + <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> |
| + <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> |
| + <value value="13" name="PERF_TP_QUADS_RECEIVED"/> |
| + <value value="14" name="PERF_TP_QUADS_OFFSET"/> |
| + <value value="15" name="PERF_TP_QUADS_SHADOW"/> |
| + <value value="16" name="PERF_TP_QUADS_ARRAY"/> |
| + <value value="17" name="PERF_TP_QUADS_GRADIENT"/> |
| + <value value="18" name="PERF_TP_QUADS_1D"/> |
| + <value value="19" name="PERF_TP_QUADS_2D"/> |
| + <value value="20" name="PERF_TP_QUADS_BUFFER"/> |
| + <value value="21" name="PERF_TP_QUADS_3D"/> |
| + <value value="22" name="PERF_TP_QUADS_CUBE"/> |
| + <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> |
| + <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> |
| + <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> |
| + <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> |
| + <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> |
| + <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> |
| + <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> |
| + <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> |
| + <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> |
| + <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> |
| + <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> |
| + <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> |
| + <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> |
| + <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> |
| + <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> |
| + <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> |
| + <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> |
| + <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> |
| + <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> |
| + <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> |
| + <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> |
| + <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> |
| + <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> |
| + <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> |
| + <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> |
| + <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> |
| + <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> |
| + <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> |
| + <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> |
| + <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> |
| + <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> |
| + <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> |
| + <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> |
| + <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> |
| +</enum> |
| + |
| +<enum name="a6xx_sp_perfcounter_select"> |
| + <value value="0" name="PERF_SP_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> |
| + <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> |
| + <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> |
| + <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> |
| + <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> |
| + <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> |
| + <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> |
| + <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> |
| + <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> |
| + <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> |
| + <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> |
| + <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> |
| + <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> |
| + <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> |
| + <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> |
| + <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> |
| + <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> |
| + <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> |
| + <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> |
| + <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> |
| + <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> |
| + <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> |
| + <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> |
| + <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> |
| + <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> |
| + <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> |
| + <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> |
| + <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> |
| + <value value="29" name="PERF_SP_LM_ATOMICS"/> |
| + <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> |
| + <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> |
| + <value value="32" name="PERF_SP_GM_ATOMICS"/> |
| + <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> |
| + <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> |
| + <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| + <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| + <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> |
| + <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> |
| + <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> |
| + <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| + <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| + <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> |
| + <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> |
| + <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> |
| + <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> |
| + <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> |
| + <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> |
| + <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> |
| + <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> |
| + <value value="50" name="PERF_SP_PIXELS_KILLED"/> |
| + <value value="51" name="PERF_SP_ICL1_REQUESTS"/> |
| + <value value="52" name="PERF_SP_ICL1_MISSES"/> |
| + <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> |
| + <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> |
| + <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> |
| + <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> |
| + <value value="57" name="PERF_SP_GPR_READ"/> |
| + <value value="58" name="PERF_SP_GPR_WRITE"/> |
| + <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| + <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| + <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> |
| + <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> |
| + <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> |
| + <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> |
| + <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> |
| + <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> |
| + <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> |
| + <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> |
| + <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> |
| + <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> |
| + <value value="71" name="PERF_SP_WORKING_EU"/> |
| + <value value="72" name="PERF_SP_ANY_EU_WORKING"/> |
| + <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> |
| + <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> |
| + <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> |
| + <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> |
| + <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> |
| + <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> |
| + <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> |
| + <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> |
| + <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> |
| + <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> |
| + <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> |
| + <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> |
| +</enum> |
| + |
| +<enum name="a6xx_rb_perfcounter_select"> |
| + <value value="0" name="PERF_RB_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> |
| + <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> |
| + <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> |
| + <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> |
| + <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> |
| + <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> |
| + <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> |
| + <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> |
| + <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> |
| + <value value="10" name="PERF_RB_Z_WORKLOAD"/> |
| + <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> |
| + <value value="12" name="PERF_RB_Z_READ"/> |
| + <value value="13" name="PERF_RB_Z_WRITE"/> |
| + <value value="14" name="PERF_RB_C_READ"/> |
| + <value value="15" name="PERF_RB_C_WRITE"/> |
| + <value value="16" name="PERF_RB_TOTAL_PASS"/> |
| + <value value="17" name="PERF_RB_Z_PASS"/> |
| + <value value="18" name="PERF_RB_Z_FAIL"/> |
| + <value value="19" name="PERF_RB_S_FAIL"/> |
| + <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> |
| + <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> |
| + <value value="22" name="PERF_RB_PS_INVOCATIONS"/> |
| + <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> |
| + <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> |
| + <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> |
| + <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> |
| + <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> |
| + <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> |
| + <value value="29" name="PERF_RB_3D_PIXELS"/> |
| + <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> |
| + <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> |
| + <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> |
| + <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> |
| + <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> |
| + <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> |
| + <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> |
| + <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> |
| + <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> |
| + <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> |
| + <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> |
| + <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> |
| + <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> |
| + <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> |
| + <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> |
| + <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> |
| + <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> |
| + <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> |
| +</enum> |
| + |
| +<enum name="a6xx_vsc_perfcounter_select"> |
| + <value value="0" name="PERF_VSC_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_VSC_WORKING_CYCLES"/> |
| + <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> |
| + <value value="3" name="PERF_VSC_EOT_NUM"/> |
| + <value value="4" name="PERF_VSC_INPUT_TILES"/> |
| +</enum> |
| + |
| +<enum name="a6xx_ccu_perfcounter_select"> |
| + <value value="0" name="PERF_CCU_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> |
| + <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> |
| + <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> |
| + <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> |
| + <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> |
| + <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> |
| + <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> |
| + <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> |
| + <value value="9" name="PERF_CCU_GMEM_READ"/> |
| + <value value="10" name="PERF_CCU_GMEM_WRITE"/> |
| + <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> |
| + <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> |
| + <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> |
| + <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> |
| + <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> |
| + <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> |
| + <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> |
| + <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> |
| + <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> |
| + <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> |
| + <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> |
| + <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> |
| + <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> |
| + <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> |
| + <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> |
| + <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> |
| + <value value="27" name="PERF_CCU_2D_RD_REQ"/> |
| + <value value="28" name="PERF_CCU_2D_WR_REQ"/> |
| +</enum> |
| + |
| +<enum name="a6xx_lrz_perfcounter_select"> |
| + <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> |
| + <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> |
| + <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> |
| + <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> |
| + <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> |
| + <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> |
| + <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> |
| + <value value="7" name="PERF_LRZ_LRZ_READ"/> |
| + <value value="8" name="PERF_LRZ_LRZ_WRITE"/> |
| + <value value="9" name="PERF_LRZ_READ_LATENCY"/> |
| + <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> |
| + <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> |
| + <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> |
| + <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> |
| + <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> |
| + <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> |
| + <value value="16" name="PERF_LRZ_TILE_KILLED"/> |
| + <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> |
| + <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> |
| + <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> |
| + <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> |
| + <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> |
| + <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> |
| + <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> |
| + <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> |
| + <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> |
| + <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> |
| + <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> |
| +</enum> |
| + |
| +<enum name="a6xx_cmp_perfcounter_select"> |
| + <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> |
| + <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> |
| + <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> |
| + <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> |
| + <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> |
| + <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> |
| + <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> |
| + <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> |
| + <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> |
| + <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> |
| + <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> |
| + <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> |
| + <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> |
| + <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> |
| + <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> |
| + <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> |
| + <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> |
| + <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> |
| + <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> |
| + <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> |
| + <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> |
| + <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> |
| + <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> |
| + <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> |
| + <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> |
| + <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> |
| + <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> |
| + <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> |
| + <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> |
| + <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> |
| + <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> |
| + <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> |
| + <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> |
| + <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> |
| + <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> |
| + <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> |
| + <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> |
| + <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> |
| + <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> |
| + <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> |
| +</enum> |
| + |
| +</database> |
| diff --git a/drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml b/drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml |
| new file mode 100644 |
| index 000000000000..661b0dd0f675 |
| --- /dev/null |
| +++ b/drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml |
| @@ -0,0 +1,223 @@ |
| +<?xml version="1.0" encoding="UTF-8"?> |
| +<database xmlns="http://nouveau.freedesktop.org/" |
| +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
| +xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| +<import file="freedreno_copyright.xml"/> |
| +<import file="adreno/adreno_common.xml"/> |
| +<import file="adreno/adreno_pm4.xml"/> |
| + |
| +<enum name="a7xx_statetype_id"> |
| + <value value="0" name="A7XX_TP0_NCTX_REG"/> |
| + <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/> |
| + <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/> |
| + <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/> |
| + <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/> |
| + <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/> |
| + <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/> |
| + <value value="9" name="A7XX_TP0_TMO_DATA"/> |
| + <value value="10" name="A7XX_TP0_SMO_DATA"/> |
| + <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/> |
| + <value value="32" name="A7XX_SP_NCTX_REG"/> |
| + <value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/> |
| + <value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/> |
| + <value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/> |
| + <value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/> |
| + <value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/> |
| + <value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/> |
| + <value value="39" name="A7XX_SP_INST_DATA"/> |
| + <value value="40" name="A7XX_SP_INST_DATA_1"/> |
| + <value value="41" name="A7XX_SP_LB_0_DATA"/> |
| + <value value="42" name="A7XX_SP_LB_1_DATA"/> |
| + <value value="43" name="A7XX_SP_LB_2_DATA"/> |
| + <value value="44" name="A7XX_SP_LB_3_DATA"/> |
| + <value value="45" name="A7XX_SP_LB_4_DATA"/> |
| + <value value="46" name="A7XX_SP_LB_5_DATA"/> |
| + <value value="47" name="A7XX_SP_LB_6_DATA"/> |
| + <value value="48" name="A7XX_SP_LB_7_DATA"/> |
| + <value value="49" name="A7XX_SP_CB_RAM"/> |
| + <value value="50" name="A7XX_SP_LB_13_DATA"/> |
| + <value value="51" name="A7XX_SP_LB_14_DATA"/> |
| + <value value="52" name="A7XX_SP_INST_TAG"/> |
| + <value value="53" name="A7XX_SP_INST_DATA_2"/> |
| + <value value="54" name="A7XX_SP_TMO_TAG"/> |
| + <value value="55" name="A7XX_SP_SMO_TAG"/> |
| + <value value="56" name="A7XX_SP_STATE_DATA"/> |
| + <value value="57" name="A7XX_SP_HWAVE_RAM"/> |
| + <value value="58" name="A7XX_SP_L0_INST_BUF"/> |
| + <value value="59" name="A7XX_SP_LB_8_DATA"/> |
| + <value value="60" name="A7XX_SP_LB_9_DATA"/> |
| + <value value="61" name="A7XX_SP_LB_10_DATA"/> |
| + <value value="62" name="A7XX_SP_LB_11_DATA"/> |
| + <value value="63" name="A7XX_SP_LB_12_DATA"/> |
| + <value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/> |
| + <value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/> |
| + <value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/> |
| + <value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/> |
| + <value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/> |
| + <value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/> |
| + <value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/> |
| + <value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/> |
| + <value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/> |
| + <value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/> |
| + <value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/> |
| + <value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> |
| + <value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> |
| + <value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/> |
| + <value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/> |
| + <value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/> |
| + <value value="82" name="A7XX_HLSQ_INST_RAM"/> |
| + <value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/> |
| + <value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/> |
| + <value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/> |
| + <value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/> |
| + <value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/> |
| + <value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> |
| + <value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> |
| + <value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/> |
| + <value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/> |
| + <value value="92" name="A7XX_HLSQ_INST_RAM_1"/> |
| + <value value="93" name="A7XX_HLSQ_STPROC_META"/> |
| + <value value="94" name="A7XX_HLSQ_BV_BE_META"/> |
| + <value value="95" name="A7XX_HLSQ_INST_RAM_2"/> |
| + <value value="96" name="A7XX_HLSQ_DATAPATH_META"/> |
| + <value value="97" name="A7XX_HLSQ_FRONTEND_META"/> |
| + <value value="98" name="A7XX_HLSQ_INDIRECT_META"/> |
| + <value value="99" name="A7XX_HLSQ_BACKEND_META"/> |
| +</enum> |
| + |
| +<enum name="a7xx_state_location"> |
| + <value value="0" name="A7XX_HLSQ_STATE"/> |
| + <value value="1" name="A7XX_HLSQ_DP"/> |
| + <value value="2" name="A7XX_SP_TOP"/> |
| + <value value="3" name="A7XX_USPTP"/> |
| + <value value="4" name="A7XX_HLSQ_DP_STR"/> |
| +</enum> |
| + |
| +<enum name="a7xx_pipe"> |
| + <value value="0" name="A7XX_PIPE_NONE"/> |
| + <value value="1" name="A7XX_PIPE_BR"/> |
| + <value value="2" name="A7XX_PIPE_BV"/> |
| + <value value="3" name="A7XX_PIPE_LPAC"/> |
| +</enum> |
| + |
| +<enum name="a7xx_cluster"> |
| + <value value="0" name="A7XX_CLUSTER_NONE"/> |
| + <value value="1" name="A7XX_CLUSTER_FE"/> |
| + <value value="2" name="A7XX_CLUSTER_SP_VS"/> |
| + <value value="3" name="A7XX_CLUSTER_PC_VS"/> |
| + <value value="4" name="A7XX_CLUSTER_GRAS"/> |
| + <value value="5" name="A7XX_CLUSTER_SP_PS"/> |
| + <value value="6" name="A7XX_CLUSTER_VPC_PS"/> |
| + <value value="7" name="A7XX_CLUSTER_PS"/> |
| +</enum> |
| + |
| +<enum name="a7xx_debugbus_id"> |
| + <value value="1" name="A7XX_DBGBUS_CP_0_0"/> |
| + <value value="2" name="A7XX_DBGBUS_CP_0_1"/> |
| + <value value="3" name="A7XX_DBGBUS_RBBM"/> |
| + <value value="5" name="A7XX_DBGBUS_GBIF_GX"/> |
| + <value value="6" name="A7XX_DBGBUS_GBIF_CX"/> |
| + <value value="7" name="A7XX_DBGBUS_HLSQ"/> |
| + <value value="9" name="A7XX_DBGBUS_UCHE_0"/> |
| + <value value="10" name="A7XX_DBGBUS_UCHE_1"/> |
| + <value value="13" name="A7XX_DBGBUS_TESS_BR"/> |
| + <value value="14" name="A7XX_DBGBUS_TESS_BV"/> |
| + <value value="17" name="A7XX_DBGBUS_PC_BR"/> |
| + <value value="18" name="A7XX_DBGBUS_PC_BV"/> |
| + <value value="21" name="A7XX_DBGBUS_VFDP_BR"/> |
| + <value value="22" name="A7XX_DBGBUS_VFDP_BV"/> |
| + <value value="25" name="A7XX_DBGBUS_VPC_BR"/> |
| + <value value="26" name="A7XX_DBGBUS_VPC_BV"/> |
| + <value value="29" name="A7XX_DBGBUS_TSE_BR"/> |
| + <value value="30" name="A7XX_DBGBUS_TSE_BV"/> |
| + <value value="33" name="A7XX_DBGBUS_RAS_BR"/> |
| + <value value="34" name="A7XX_DBGBUS_RAS_BV"/> |
| + <value value="37" name="A7XX_DBGBUS_VSC"/> |
| + <value value="39" name="A7XX_DBGBUS_COM_0"/> |
| + <value value="43" name="A7XX_DBGBUS_LRZ_BR"/> |
| + <value value="44" name="A7XX_DBGBUS_LRZ_BV"/> |
| + <value value="47" name="A7XX_DBGBUS_UFC_0"/> |
| + <value value="48" name="A7XX_DBGBUS_UFC_1"/> |
| + <value value="55" name="A7XX_DBGBUS_GMU_GX"/> |
| + <value value="59" name="A7XX_DBGBUS_DBGC"/> |
| + <value value="60" name="A7XX_DBGBUS_CX"/> |
| + <value value="61" name="A7XX_DBGBUS_GMU_CX"/> |
| + <value value="62" name="A7XX_DBGBUS_GPC_BR"/> |
| + <value value="63" name="A7XX_DBGBUS_GPC_BV"/> |
| + <value value="66" name="A7XX_DBGBUS_LARC"/> |
| + <value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/> |
| + <value value="70" name="A7XX_DBGBUS_RB_0"/> |
| + <value value="71" name="A7XX_DBGBUS_RB_1"/> |
| + <value value="72" name="A7XX_DBGBUS_RB_2"/> |
| + <value value="73" name="A7XX_DBGBUS_RB_3"/> |
| + <value value="74" name="A7XX_DBGBUS_RB_4"/> |
| + <value value="75" name="A7XX_DBGBUS_RB_5"/> |
| + <value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/> |
| + <value value="106" name="A7XX_DBGBUS_CCU_0"/> |
| + <value value="107" name="A7XX_DBGBUS_CCU_1"/> |
| + <value value="108" name="A7XX_DBGBUS_CCU_2"/> |
| + <value value="109" name="A7XX_DBGBUS_CCU_3"/> |
| + <value value="110" name="A7XX_DBGBUS_CCU_4"/> |
| + <value value="111" name="A7XX_DBGBUS_CCU_5"/> |
| + <value value="138" name="A7XX_DBGBUS_VFD_BR_0"/> |
| + <value value="139" name="A7XX_DBGBUS_VFD_BR_1"/> |
| + <value value="140" name="A7XX_DBGBUS_VFD_BR_2"/> |
| + <value value="141" name="A7XX_DBGBUS_VFD_BR_3"/> |
| + <value value="142" name="A7XX_DBGBUS_VFD_BR_4"/> |
| + <value value="143" name="A7XX_DBGBUS_VFD_BR_5"/> |
| + <value value="144" name="A7XX_DBGBUS_VFD_BR_6"/> |
| + <value value="145" name="A7XX_DBGBUS_VFD_BR_7"/> |
| + <value value="202" name="A7XX_DBGBUS_VFD_BV_0"/> |
| + <value value="203" name="A7XX_DBGBUS_VFD_BV_1"/> |
| + <value value="204" name="A7XX_DBGBUS_VFD_BV_2"/> |
| + <value value="205" name="A7XX_DBGBUS_VFD_BV_3"/> |
| + <value value="234" name="A7XX_DBGBUS_USP_0"/> |
| + <value value="235" name="A7XX_DBGBUS_USP_1"/> |
| + <value value="236" name="A7XX_DBGBUS_USP_2"/> |
| + <value value="237" name="A7XX_DBGBUS_USP_3"/> |
| + <value value="238" name="A7XX_DBGBUS_USP_4"/> |
| + <value value="239" name="A7XX_DBGBUS_USP_5"/> |
| + <value value="266" name="A7XX_DBGBUS_TP_0"/> |
| + <value value="267" name="A7XX_DBGBUS_TP_1"/> |
| + <value value="268" name="A7XX_DBGBUS_TP_2"/> |
| + <value value="269" name="A7XX_DBGBUS_TP_3"/> |
| + <value value="270" name="A7XX_DBGBUS_TP_4"/> |
| + <value value="271" name="A7XX_DBGBUS_TP_5"/> |
| + <value value="272" name="A7XX_DBGBUS_TP_6"/> |
| + <value value="273" name="A7XX_DBGBUS_TP_7"/> |
| + <value value="274" name="A7XX_DBGBUS_TP_8"/> |
| + <value value="275" name="A7XX_DBGBUS_TP_9"/> |
| + <value value="276" name="A7XX_DBGBUS_TP_10"/> |
| + <value value="277" name="A7XX_DBGBUS_TP_11"/> |
| + <value value="330" name="A7XX_DBGBUS_USPTP_0"/> |
| + <value value="331" name="A7XX_DBGBUS_USPTP_1"/> |
| + <value value="332" name="A7XX_DBGBUS_USPTP_2"/> |
| + <value value="333" name="A7XX_DBGBUS_USPTP_3"/> |
| + <value value="334" name="A7XX_DBGBUS_USPTP_4"/> |
| + <value value="335" name="A7XX_DBGBUS_USPTP_5"/> |
| + <value value="336" name="A7XX_DBGBUS_USPTP_6"/> |
| + <value value="337" name="A7XX_DBGBUS_USPTP_7"/> |
| + <value value="338" name="A7XX_DBGBUS_USPTP_8"/> |
| + <value value="339" name="A7XX_DBGBUS_USPTP_9"/> |
| + <value value="340" name="A7XX_DBGBUS_USPTP_10"/> |
| + <value value="341" name="A7XX_DBGBUS_USPTP_11"/> |
| + <value value="396" name="A7XX_DBGBUS_CCHE_0"/> |
| + <value value="397" name="A7XX_DBGBUS_CCHE_1"/> |
| + <value value="398" name="A7XX_DBGBUS_CCHE_2"/> |
| + <value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/> |
| + <value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/> |
| + <value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/> |
| + <value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/> |
| + <value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/> |
| + <value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/> |
| + <value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/> |
| + <value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/> |
| + <value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/> |
| + <value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/> |
| + <value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/> |
| + <value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/> |
| + <value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/> |
| + <value value="447" name="A7XX_DBGBUS_CGC_CORE"/> |
| +</enum> |
| + |
| +</database> |
| diff --git a/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.xml b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.xml |
| new file mode 100644 |
| index 000000000000..9bf78b0a854b |
| --- /dev/null |
| +++ b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.xml |
| @@ -0,0 +1,1030 @@ |
| +<?xml version="1.0" encoding="UTF-8"?> |
| +<database xmlns="http://nouveau.freedesktop.org/" |
| +xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
| +xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| +<import file="freedreno_copyright.xml"/> |
| +<import file="adreno/adreno_common.xml"/> |
| +<import file="adreno/adreno_pm4.xml"/> |
| + |
| +<enum name="a7xx_cp_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_CP_ALWAYS_COUNT"/> |
| + <value value="1" name="A7XX_PERF_CP_BUSY_GFX_CORE_IDLE"/> |
| + <value value="2" name="A7XX_PERF_CP_BUSY_CYCLES"/> |
| + <value value="3" name="A7XX_PERF_CP_NUM_PREEMPTIONS"/> |
| + <value value="4" name="A7XX_PERF_CP_PREEMPTION_REACTION_DELAY"/> |
| + <value value="5" name="A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> |
| + <value value="6" name="A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> |
| + <value value="7" name="A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> |
| + <value value="8" name="A7XX_PERF_CP_PREDICATED_DRAWS_KILLED"/> |
| + <value value="9" name="A7XX_PERF_CP_MODE_SWITCH"/> |
| + <value value="10" name="A7XX_PERF_CP_ZPASS_DONE"/> |
| + <value value="11" name="A7XX_PERF_CP_CONTEXT_DONE"/> |
| + <value value="12" name="A7XX_PERF_CP_CACHE_FLUSH"/> |
| + <value value="13" name="A7XX_PERF_CP_LONG_PREEMPTIONS"/> |
| + <value value="14" name="A7XX_PERF_CP_SQE_I_CACHE_STARVE"/> |
| + <value value="15" name="A7XX_PERF_CP_SQE_IDLE"/> |
| + <value value="16" name="A7XX_PERF_CP_SQE_PM4_STARVE_RB_IB"/> |
| + <value value="17" name="A7XX_PERF_CP_SQE_PM4_STARVE_SDS"/> |
| + <value value="18" name="A7XX_PERF_CP_SQE_MRB_STARVE"/> |
| + <value value="19" name="A7XX_PERF_CP_SQE_RRB_STARVE"/> |
| + <value value="20" name="A7XX_PERF_CP_SQE_VSD_STARVE"/> |
| + <value value="21" name="A7XX_PERF_CP_VSD_DECODE_STARVE"/> |
| + <value value="22" name="A7XX_PERF_CP_SQE_PIPE_OUT_STALL"/> |
| + <value value="23" name="A7XX_PERF_CP_SQE_SYNC_STALL"/> |
| + <value value="24" name="A7XX_PERF_CP_SQE_PM4_WFI_STALL"/> |
| + <value value="25" name="A7XX_PERF_CP_SQE_SYS_WFI_STALL"/> |
| + <value value="26" name="A7XX_PERF_CP_SQE_T4_EXEC"/> |
| + <value value="27" name="A7XX_PERF_CP_SQE_LOAD_STATE_EXEC"/> |
| + <value value="28" name="A7XX_PERF_CP_SQE_SAVE_SDS_STATE"/> |
| + <value value="29" name="A7XX_PERF_CP_SQE_DRAW_EXEC"/> |
| + <value value="30" name="A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> |
| + <value value="31" name="A7XX_PERF_CP_SQE_EXEC_PROFILED"/> |
| + <value value="32" name="A7XX_PERF_CP_MEMORY_POOL_EMPTY"/> |
| + <value value="33" name="A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL"/> |
| + <value value="34" name="A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> |
| + <value value="35" name="A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> |
| + <value value="36" name="A7XX_PERF_CP_AHB_STALL_SQE_GMU"/> |
| + <value value="37" name="A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER"/> |
| + <value value="38" name="A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER"/> |
| + <value value="39" name="A7XX_PERF_CP_CLUSTER0_EMPTY"/> |
| + <value value="40" name="A7XX_PERF_CP_CLUSTER1_EMPTY"/> |
| + <value value="41" name="A7XX_PERF_CP_CLUSTER2_EMPTY"/> |
| + <value value="42" name="A7XX_PERF_CP_CLUSTER3_EMPTY"/> |
| + <value value="43" name="A7XX_PERF_CP_CLUSTER4_EMPTY"/> |
| + <value value="44" name="A7XX_PERF_CP_CLUSTER5_EMPTY"/> |
| + <value value="45" name="A7XX_PERF_CP_PM4_DATA"/> |
| + <value value="46" name="A7XX_PERF_CP_PM4_HEADERS"/> |
| + <value value="47" name="A7XX_PERF_CP_VBIF_READ_BEATS"/> |
| + <value value="48" name="A7XX_PERF_CP_VBIF_WRITE_BEATS"/> |
| + <value value="49" name="A7XX_PERF_CP_SQE_INSTR_COUNTER"/> |
| + <value value="50" name="A7XX_PERF_CP_RESERVED_50"/> |
| + <value value="51" name="A7XX_PERF_CP_RESERVED_51"/> |
| + <value value="52" name="A7XX_PERF_CP_RESERVED_52"/> |
| + <value value="53" name="A7XX_PERF_CP_RESERVED_53"/> |
| + <value value="54" name="A7XX_PERF_CP_RESERVED_54"/> |
| + <value value="55" name="A7XX_PERF_CP_RESERVED_55"/> |
| + <value value="56" name="A7XX_PERF_CP_RESERVED_56"/> |
| + <value value="57" name="A7XX_PERF_CP_RESERVED_57"/> |
| + <value value="58" name="A7XX_PERF_CP_RESERVED_58"/> |
| + <value value="59" name="A7XX_PERF_CP_RESERVED_59"/> |
| + <value value="60" name="A7XX_PERF_CP_CLUSTER0_FULL"/> |
| + <value value="61" name="A7XX_PERF_CP_CLUSTER1_FULL"/> |
| + <value value="62" name="A7XX_PERF_CP_CLUSTER2_FULL"/> |
| + <value value="63" name="A7XX_PERF_CP_CLUSTER3_FULL"/> |
| + <value value="64" name="A7XX_PERF_CP_CLUSTER4_FULL"/> |
| + <value value="65" name="A7XX_PERF_CP_CLUSTER5_FULL"/> |
| + <value value="66" name="A7XX_PERF_CP_CLUSTER6_FULL"/> |
| + <value value="67" name="A7XX_PERF_CP_CLUSTER6_EMPTY"/> |
| + <value value="68" name="A7XX_PERF_CP_ICACHE_MISSES"/> |
| + <value value="69" name="A7XX_PERF_CP_ICACHE_HITS"/> |
| + <value value="70" name="A7XX_PERF_CP_ICACHE_STALL"/> |
| + <value value="71" name="A7XX_PERF_CP_DCACHE_MISSES"/> |
| + <value value="72" name="A7XX_PERF_CP_DCACHE_HITS"/> |
| + <value value="73" name="A7XX_PERF_CP_DCACHE_STALLS"/> |
| + <value value="74" name="A7XX_PERF_CP_AQE_SQE_STALL"/> |
| + <value value="75" name="A7XX_PERF_CP_SQE_AQE_STARVE"/> |
| + <value value="76" name="A7XX_PERF_CP_PREEMPT_LATENCY"/> |
| + <value value="77" name="A7XX_PERF_CP_SQE_MD8_STALL_CYCLES"/> |
| + <value value="78" name="A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES"/> |
| + <value value="79" name="A7XX_PERF_CP_AQE_NUM_AS_CHUNKS"/> |
| + <value value="80" name="A7XX_PERF_CP_AQE_NUM_MS_CHUNKS"/> |
| +</enum> |
| + |
| +<enum name="a7xx_rbbm_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_RBBM_ALWAYS_COUNT"/> |
| + <value value="1" name="A7XX_PERF_RBBM_ALWAYS_ON"/> |
| + <value value="2" name="A7XX_PERF_RBBM_TSE_BUSY"/> |
| + <value value="3" name="A7XX_PERF_RBBM_RAS_BUSY"/> |
| + <value value="4" name="A7XX_PERF_RBBM_PC_DCALL_BUSY"/> |
| + <value value="5" name="A7XX_PERF_RBBM_PC_VSD_BUSY"/> |
| + <value value="6" name="A7XX_PERF_RBBM_STATUS_MASKED"/> |
| + <value value="7" name="A7XX_PERF_RBBM_COM_BUSY"/> |
| + <value value="8" name="A7XX_PERF_RBBM_DCOM_BUSY"/> |
| + <value value="9" name="A7XX_PERF_RBBM_VBIF_BUSY"/> |
| + <value value="10" name="A7XX_PERF_RBBM_VSC_BUSY"/> |
| + <value value="11" name="A7XX_PERF_RBBM_TESS_BUSY"/> |
| + <value value="12" name="A7XX_PERF_RBBM_UCHE_BUSY"/> |
| + <value value="13" name="A7XX_PERF_RBBM_HLSQ_BUSY"/> |
| +</enum> |
| + |
| +<enum name="a7xx_pc_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_PC_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_PC_WORKING_CYCLES"/> |
| + <value value="2" name="A7XX_PERF_PC_STALL_CYCLES_VFD"/> |
| + <value value="3" name="A7XX_PERF_PC_RESERVED"/> |
| + <value value="4" name="A7XX_PERF_PC_STALL_CYCLES_VPC"/> |
| + <value value="5" name="A7XX_PERF_PC_STALL_CYCLES_UCHE"/> |
| + <value value="6" name="A7XX_PERF_PC_STALL_CYCLES_TESS"/> |
| + <value value="7" name="A7XX_PERF_PC_STALL_CYCLES_VFD_ONLY"/> |
| + <value value="8" name="A7XX_PERF_PC_STALL_CYCLES_VPC_ONLY"/> |
| + <value value="9" name="A7XX_PERF_PC_PASS1_TF_STALL_CYCLES"/> |
| + <value value="10" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_INDEX"/> |
| + <value value="11" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> |
| + <value value="12" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> |
| + <value value="13" name="A7XX_PERF_PC_STARVE_CYCLES_DI"/> |
| + <value value="14" name="A7XX_PERF_PC_VIS_STREAMS_LOADED"/> |
| + <value value="15" name="A7XX_PERF_PC_INSTANCES"/> |
| + <value value="16" name="A7XX_PERF_PC_VPC_PRIMITIVES"/> |
| + <value value="17" name="A7XX_PERF_PC_DEAD_PRIM"/> |
| + <value value="18" name="A7XX_PERF_PC_LIVE_PRIM"/> |
| + <value value="19" name="A7XX_PERF_PC_VERTEX_HITS"/> |
| + <value value="20" name="A7XX_PERF_PC_IA_VERTICES"/> |
| + <value value="21" name="A7XX_PERF_PC_IA_PRIMITIVES"/> |
| + <value value="22" name="A7XX_PERF_PC_RESERVED_22"/> |
| + <value value="23" name="A7XX_PERF_PC_HS_INVOCATIONS"/> |
| + <value value="24" name="A7XX_PERF_PC_DS_INVOCATIONS"/> |
| + <value value="25" name="A7XX_PERF_PC_VS_INVOCATIONS"/> |
| + <value value="26" name="A7XX_PERF_PC_GS_INVOCATIONS"/> |
| + <value value="27" name="A7XX_PERF_PC_DS_PRIMITIVES"/> |
| + <value value="28" name="A7XX_PERF_PC_3D_DRAWCALLS"/> |
| + <value value="29" name="A7XX_PERF_PC_2D_DRAWCALLS"/> |
| + <value value="30" name="A7XX_PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> |
| + <value value="31" name="A7XX_PERF_PC_TESS_BUSY_CYCLES"/> |
| + <value value="32" name="A7XX_PERF_PC_TESS_WORKING_CYCLES"/> |
| + <value value="33" name="A7XX_PERF_PC_TESS_STALL_CYCLES_PC"/> |
| + <value value="34" name="A7XX_PERF_PC_TESS_STARVE_CYCLES_PC"/> |
| + <value value="35" name="A7XX_PERF_PC_TESS_SINGLE_PRIM_CYCLES"/> |
| + <value value="36" name="A7XX_PERF_PC_TESS_PC_UV_TRANS"/> |
| + <value value="37" name="A7XX_PERF_PC_TESS_PC_UV_PATCHES"/> |
| + <value value="38" name="A7XX_PERF_PC_TESS_FACTOR_TRANS"/> |
| + <value value="39" name="A7XX_PERF_PC_TAG_CHECKED_VERTICES"/> |
| + <value value="40" name="A7XX_PERF_PC_MESH_VS_WAVES"/> |
| + <value value="41" name="A7XX_PERF_PC_MESH_DRAWS"/> |
| + <value value="42" name="A7XX_PERF_PC_MESH_DEAD_DRAWS"/> |
| + <value value="43" name="A7XX_PERF_PC_MESH_MVIS_EN_DRAWS"/> |
| + <value value="44" name="A7XX_PERF_PC_MESH_DEAD_PRIM"/> |
| + <value value="45" name="A7XX_PERF_PC_MESH_LIVE_PRIM"/> |
| + <value value="46" name="A7XX_PERF_PC_MESH_PA_EN_PRIM"/> |
| + <value value="47" name="A7XX_PERF_PC_STARVE_CYCLES_FOR_MVIS_STREAM"/> |
| + <value value="48" name="A7XX_PERF_PC_STARVE_CYCLES_PREDRAW"/> |
| + <value value="49" name="A7XX_PERF_PC_STALL_CYCLES_COMPUTE_GFX"/> |
| + <value value="50" name="A7XX_PERF_PC_STALL_CYCLES_GFX_COMPUTE"/> |
| + <value value="51" name="A7XX_PERF_PC_TESS_PC_MULTI_PATCH_TRANS"/> |
| +</enum> |
| + |
| +<enum name="a7xx_vfd_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_VFD_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_VFD_STALL_CYCLES_UCHE"/> |
| + <value value="2" name="A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> |
| + <value value="3" name="A7XX_PERF_VFD_STALL_CYCLES_SP_INFO"/> |
| + <value value="4" name="A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR"/> |
| + <value value="5" name="A7XX_PERF_VFD_STARVE_CYCLES_UCHE"/> |
| + <value value="6" name="A7XX_PERF_VFD_RBUFFER_FULL"/> |
| + <value value="7" name="A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL"/> |
| + <value value="8" name="A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> |
| + <value value="9" name="A7XX_PERF_VFD_NUM_ATTRIBUTES"/> |
| + <value value="10" name="A7XX_PERF_VFD_UPPER_SHADER_FIBERS"/> |
| + <value value="11" name="A7XX_PERF_VFD_LOWER_SHADER_FIBERS"/> |
| + <value value="12" name="A7XX_PERF_VFD_MODE_0_FIBERS"/> |
| + <value value="13" name="A7XX_PERF_VFD_MODE_1_FIBERS"/> |
| + <value value="14" name="A7XX_PERF_VFD_MODE_2_FIBERS"/> |
| + <value value="15" name="A7XX_PERF_VFD_MODE_3_FIBERS"/> |
| + <value value="16" name="A7XX_PERF_VFD_MODE_4_FIBERS"/> |
| + <value value="17" name="A7XX_PERF_VFD_TOTAL_VERTICES"/> |
| + <value value="18" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD"/> |
| + <value value="19" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> |
| + <value value="20" name="A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG"/> |
| + <value value="21" name="A7XX_PERF_VFDP_STARVE_CYCLES_PC"/> |
| + <value value="22" name="A7XX_PERF_VFDP_VS_STAGE_WAVES"/> |
| + <value value="23" name="A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE"/> |
| + <value value="24" name="A7XX_PERF_VFD_STALL_CYCLES_CBSYNC"/> |
| +</enum> |
| + |
| +<enum name="a7xx_hlsq_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_HLSQ_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_HLSQ_STALL_CYCLES_UCHE"/> |
| + <value value="2" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE"/> |
| + <value value="3" name="A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> |
| + <value value="4" name="A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES"/> |
| + <value value="5" name="A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT"/> |
| + <value value="6" name="A7XX_PERF_HLSQ_RESERVED_6"/> |
| + <value value="7" name="A7XX_PERF_HLSQ_RESERVED_7"/> |
| + <value value="8" name="A7XX_PERF_HLSQ_RESERVED_8"/> |
| + <value value="9" name="A7XX_PERF_HLSQ_RESERVED_9"/> |
| + <value value="10" name="A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS"/> |
| + <value value="11" name="A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> |
| + <value value="12" name="A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> |
| + <value value="13" name="A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> |
| + <value value="14" name="A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> |
| + <value value="15" name="A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> |
| + <value value="16" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> |
| + <value value="17" name="A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> |
| + <value value="18" name="A7XX_PERF_HLSQ_STALL_CYCLES_VPC"/> |
| + <value value="19" name="A7XX_PERF_HLSQ_RESERVED_19"/> |
| + <value value="20" name="A7XX_PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> |
| + <value value="21" name="A7XX_PERF_HLSQ_VSBR_STALL_CYCLES"/> |
| + <value value="22" name="A7XX_PERF_HLSQ_FS_STALL_CYCLES"/> |
| + <value value="23" name="A7XX_PERF_HLSQ_LPAC_STALL_CYCLES"/> |
| + <value value="24" name="A7XX_PERF_HLSQ_BV_STALL_CYCLES"/> |
| + <value value="25" name="A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES"/> |
| + <value value="26" name="A7XX_PERF_HLSQ_FS_DEREF_CYCLES"/> |
| + <value value="27" name="A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES"/> |
| + <value value="28" name="A7XX_PERF_HLSQ_BV_DEREF_CYCLES"/> |
| + <value value="29" name="A7XX_PERF_HLSQ_VSBR_S2W_CYCLES"/> |
| + <value value="30" name="A7XX_PERF_HLSQ_FS_S2W_CYCLES"/> |
| + <value value="31" name="A7XX_PERF_HLSQ_LPAC_S2W_CYCLES"/> |
| + <value value="32" name="A7XX_PERF_HLSQ_BV_S2W_CYCLES"/> |
| + <value value="33" name="A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W"/> |
| + <value value="34" name="A7XX_PERF_HLSQ_FS_WAIT_VS_S2W"/> |
| + <value value="35" name="A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W"/> |
| + <value value="36" name="A7XX_PERF_HLSQ_BV_WAIT_FS_S2W"/> |
| + <value value="37" name="A7XX_PERF_HLSQ_VS_WAIT_CONST_RESOURCE"/> |
| + <value value="38" name="A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W"/> |
| + <value value="39" name="A7XX_PERF_HLSQ_FS_STARVING_SP"/> |
| + <value value="40" name="A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING"/> |
| + <value value="41" name="A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING"/> |
| + <value value="42" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS"/> |
| + <value value="43" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS"/> |
| + <value value="44" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS"/> |
| + <value value="45" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS"/> |
| + <value value="46" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV"/> |
| + <value value="47" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV"/> |
| + <value value="48" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC"/> |
| + <value value="49" name="A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC"/> |
| + <value value="50" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS"/> |
| + <value value="51" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS"/> |
| + <value value="52" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV"/> |
| + <value value="53" name="A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC"/> |
| + <value value="54" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS"/> |
| + <value value="55" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS"/> |
| + <value value="56" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV"/> |
| + <value value="57" name="A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC"/> |
| +</enum> |
| + |
| +<enum name="a7xx_vpc_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_VPC_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_VPC_WORKING_CYCLES"/> |
| + <value value="2" name="A7XX_PERF_VPC_STALL_CYCLES_UCHE"/> |
| + <value value="3" name="A7XX_PERF_VPC_STALL_CYCLES_VFD_WACK"/> |
| + <value value="4" name="A7XX_PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> |
| + <value value="5" name="A7XX_PERF_VPC_RESERVED_5"/> |
| + <value value="6" name="A7XX_PERF_VPC_STALL_CYCLES_SP_LM"/> |
| + <value value="7" name="A7XX_PERF_VPC_STARVE_CYCLES_SP"/> |
| + <value value="8" name="A7XX_PERF_VPC_STARVE_CYCLES_LRZ"/> |
| + <value value="9" name="A7XX_PERF_VPC_PC_PRIMITIVES"/> |
| + <value value="10" name="A7XX_PERF_VPC_SP_COMPONENTS"/> |
| + <value value="11" name="A7XX_PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> |
| + <value value="12" name="A7XX_PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> |
| + <value value="13" name="A7XX_PERF_VPC_RB_VISIBLE_PRIMITIVES"/> |
| + <value value="14" name="A7XX_PERF_VPC_LM_TRANSACTION"/> |
| + <value value="15" name="A7XX_PERF_VPC_STREAMOUT_TRANSACTION"/> |
| + <value value="16" name="A7XX_PERF_VPC_VS_BUSY_CYCLES"/> |
| + <value value="17" name="A7XX_PERF_VPC_PS_BUSY_CYCLES"/> |
| + <value value="18" name="A7XX_PERF_VPC_VS_WORKING_CYCLES"/> |
| + <value value="19" name="A7XX_PERF_VPC_PS_WORKING_CYCLES"/> |
| + <value value="20" name="A7XX_PERF_VPC_STARVE_CYCLES_RB"/> |
| + <value value="21" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_POS"/> |
| + <value value="22" name="A7XX_PERF_VPC_WIT_FULL_CYCLES"/> |
| + <value value="23" name="A7XX_PERF_VPC_VPCRAM_FULL_CYCLES"/> |
| + <value value="24" name="A7XX_PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> |
| + <value value="25" name="A7XX_PERF_VPC_NUM_VPCRAM_WRITE"/> |
| + <value value="26" name="A7XX_PERF_VPC_NUM_VPCRAM_READ_SO"/> |
| + <value value="27" name="A7XX_PERF_VPC_NUM_ATTR_REQ_LM"/> |
| + <value value="28" name="A7XX_PERF_VPC_STALL_CYCLE_TSE"/> |
| + <value value="29" name="A7XX_PERF_VPC_TSE_PRIMITIVES"/> |
| + <value value="30" name="A7XX_PERF_VPC_GS_PRIMITIVES"/> |
| + <value value="31" name="A7XX_PERF_VPC_TSE_TRANSACTIONS"/> |
| + <value value="32" name="A7XX_PERF_VPC_STALL_CYCLES_CCU"/> |
| + <value value="33" name="A7XX_PERF_VPC_NUM_WM_HIT"/> |
| + <value value="34" name="A7XX_PERF_VPC_STALL_DQ_WACK"/> |
| + <value value="35" name="A7XX_PERF_VPC_STALL_CYCLES_CCHE"/> |
| + <value value="36" name="A7XX_PERF_VPC_STARVE_CYCLES_CCHE"/> |
| + <value value="37" name="A7XX_PERF_VPC_NUM_PA_REQ"/> |
| + <value value="38" name="A7XX_PERF_VPC_NUM_LM_REQ_HIT"/> |
| + <value value="39" name="A7XX_PERF_VPC_CCHE_REQBUF_FULL"/> |
| + <value value="40" name="A7XX_PERF_VPC_STALL_CYCLES_LM_ACK"/> |
| + <value value="41" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_FE"/> |
| + <value value="42" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_PCVS"/> |
| + <value value="43" name="A7XX_PERF_VPC_STALL_CYCLES_PRG_END_VPCPS"/> |
| +</enum> |
| + |
| +<enum name="a7xx_tse_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_TSE_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_TSE_CLIPPING_CYCLES"/> |
| + <value value="2" name="A7XX_PERF_TSE_STALL_CYCLES_RAS"/> |
| + <value value="3" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> |
| + <value value="4" name="A7XX_PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> |
| + <value value="5" name="A7XX_PERF_TSE_STARVE_CYCLES_PC"/> |
| + <value value="6" name="A7XX_PERF_TSE_INPUT_PRIM"/> |
| + <value value="7" name="A7XX_PERF_TSE_INPUT_NULL_PRIM"/> |
| + <value value="8" name="A7XX_PERF_TSE_TRIVAL_REJ_PRIM"/> |
| + <value value="9" name="A7XX_PERF_TSE_CLIPPED_PRIM"/> |
| + <value value="10" name="A7XX_PERF_TSE_ZERO_AREA_PRIM"/> |
| + <value value="11" name="A7XX_PERF_TSE_FACENESS_CULLED_PRIM"/> |
| + <value value="12" name="A7XX_PERF_TSE_ZERO_PIXEL_PRIM"/> |
| + <value value="13" name="A7XX_PERF_TSE_OUTPUT_NULL_PRIM"/> |
| + <value value="14" name="A7XX_PERF_TSE_OUTPUT_VISIBLE_PRIM"/> |
| + <value value="15" name="A7XX_PERF_TSE_CINVOCATION"/> |
| + <value value="16" name="A7XX_PERF_TSE_CPRIMITIVES"/> |
| + <value value="17" name="A7XX_PERF_TSE_2D_INPUT_PRIM"/> |
| + <value value="18" name="A7XX_PERF_TSE_2D_ALIVE_CYCLES"/> |
| + <value value="19" name="A7XX_PERF_TSE_CLIP_PLANES"/> |
| +</enum> |
| + |
| +<enum name="a7xx_ras_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_RAS_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> |
| + <value value="2" name="A7XX_PERF_RAS_STALL_CYCLES_LRZ"/> |
| + <value value="3" name="A7XX_PERF_RAS_STARVE_CYCLES_TSE"/> |
| + <value value="4" name="A7XX_PERF_RAS_SUPER_TILES"/> |
| + <value value="5" name="A7XX_PERF_RAS_8X4_TILES"/> |
| + <value value="6" name="A7XX_PERF_RAS_MASKGEN_ACTIVE"/> |
| + <value value="7" name="A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES"/> |
| + <value value="8" name="A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES"/> |
| + <value value="9" name="A7XX_PERF_RAS_PRIM_KILLED_INVISILBE"/> |
| + <value value="10" name="A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> |
| + <value value="11" name="A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> |
| + <value value="12" name="A7XX_PERF_RAS_BLOCKS"/> |
| + <value value="13" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_l2"/> |
| + <value value="14" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_l2"/> |
| + <value value="15" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_l2"/> |
| + <value value="16" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_l2"/> |
| + <value value="17" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_l2"/> |
| + <value value="18" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_l2"/> |
| + <value value="19" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_l2"/> |
| + <value value="20" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_l2"/> |
| + <value value="21" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_l2"/> |
| + <value value="22" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_l2"/> |
| + <value value="23" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_l2"/> |
| + <value value="24" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_l2"/> |
| + <value value="25" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_l2"/> |
| + <value value="26" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_l2"/> |
| + <value value="27" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_l2"/> |
| + <value value="28" name="A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_l2"/> |
| + <value value="29" name="A7XX_PERF_RAS_FALSE_PARTIAL_STILE"/> |
| + |
| +</enum> |
| + |
| +<enum name="a7xx_uche_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_UCHE_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_UCHE_STALL_CYCLES_ARBITER"/> |
| + <value value="2" name="A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES"/> |
| + <value value="3" name="A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES"/> |
| + <value value="4" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_TP"/> |
| + <value value="5" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD"/> |
| + <value value="6" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> |
| + <value value="7" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ"/> |
| + <value value="8" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_SP"/> |
| + <value value="9" name="A7XX_PERF_UCHE_READ_REQUESTS_TP"/> |
| + <value value="10" name="A7XX_PERF_UCHE_READ_REQUESTS_VFD"/> |
| + <value value="11" name="A7XX_PERF_UCHE_READ_REQUESTS_HLSQ"/> |
| + <value value="12" name="A7XX_PERF_UCHE_READ_REQUESTS_LRZ"/> |
| + <value value="13" name="A7XX_PERF_UCHE_READ_REQUESTS_SP"/> |
| + <value value="14" name="A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ"/> |
| + <value value="15" name="A7XX_PERF_UCHE_WRITE_REQUESTS_SP"/> |
| + <value value="16" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VPC"/> |
| + <value value="17" name="A7XX_PERF_UCHE_WRITE_REQUESTS_VSC"/> |
| + <value value="18" name="A7XX_PERF_UCHE_EVICTS"/> |
| + <value value="19" name="A7XX_PERF_UCHE_BANK_REQ0"/> |
| + <value value="20" name="A7XX_PERF_UCHE_BANK_REQ1"/> |
| + <value value="21" name="A7XX_PERF_UCHE_BANK_REQ2"/> |
| + <value value="22" name="A7XX_PERF_UCHE_BANK_REQ3"/> |
| + <value value="23" name="A7XX_PERF_UCHE_BANK_REQ4"/> |
| + <value value="24" name="A7XX_PERF_UCHE_BANK_REQ5"/> |
| + <value value="25" name="A7XX_PERF_UCHE_BANK_REQ6"/> |
| + <value value="26" name="A7XX_PERF_UCHE_BANK_REQ7"/> |
| + <value value="27" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0"/> |
| + <value value="28" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1"/> |
| + <value value="29" name="A7XX_PERF_UCHE_GMEM_READ_BEATS"/> |
| + <value value="30" name="A7XX_PERF_UCHE_TPH_REF_FULL"/> |
| + <value value="31" name="A7XX_PERF_UCHE_TPH_VICTIM_FULL"/> |
| + <value value="32" name="A7XX_PERF_UCHE_TPH_EXT_FULL"/> |
| + <value value="33" name="A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA"/> |
| + <value value="34" name="A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES"/> |
| + <value value="35" name="A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES"/> |
| + <value value="36" name="A7XX_PERF_UCHE_VBIF_READ_BEATS_PC"/> |
| + <value value="37" name="A7XX_PERF_UCHE_READ_REQUESTS_PC"/> |
| + <value value="38" name="A7XX_PERF_UCHE_RAM_READ_REQ"/> |
| + <value value="39" name="A7XX_PERF_UCHE_RAM_WRITE_REQ"/> |
| + <value value="40" name="A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP"/> |
| + <value value="41" name="A7XX_PERF_UCHE_STALL_CYCLES_DECMP"/> |
| + <value value="42" name="A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF"/> |
| + <value value="43" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC"/> |
| + <value value="44" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_NONUBWC"/> |
| + <value value="45" name="A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM"/> |
| + <value value="46" name="A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS_KAILUA"/> |
| + <value value="47" name="A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS_KAILUA"/> |
| + <value value="48" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE"/> |
| + <value value="49" name="A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER_KAILUA"/> |
| + <value value="50" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE"/> |
| + <value value="51" name="A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS"/> |
| + <value value="52" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0"/> |
| + <value value="53" name="A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1"/> |
| + <value value="54" name="A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL"/> |
| + <value value="55" name="A7XX_PERF_UCHE_CCHE_DPH_QUEUE_FULL"/> |
| + <value value="56" name="A7XX_PERF_UCHE_GMEM_WRITE_BEATS"/> |
| + <value value="57" name="A7XX_PERF_UCHE_UBWC_READ_BEATS"/> |
| + <value value="58" name="A7XX_PERF_UCHE_UBWC_WRITE_BEATS"/> |
| +</enum> |
| + |
| +<enum name="a7xx_tp_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_TP_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_TP_STALL_CYCLES_UCHE"/> |
| + <value value="2" name="A7XX_PERF_TP_LATENCY_CYCLES"/> |
| + <value value="3" name="A7XX_PERF_TP_LATENCY_TRANS"/> |
| + <value value="4" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES"/> |
| + <value value="5" name="A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES"/> |
| + <value value="6" name="A7XX_PERF_TP_L1_CACHELINE_REQUESTS"/> |
| + <value value="7" name="A7XX_PERF_TP_L1_CACHELINE_MISSES"/> |
| + <value value="8" name="A7XX_PERF_TP_SP_TP_TRANS"/> |
| + <value value="9" name="A7XX_PERF_TP_TP_SP_TRANS"/> |
| + <value value="10" name="A7XX_PERF_TP_OUTPUT_PIXELS"/> |
| + <value value="11" name="A7XX_PERF_TP_FILTER_WORKLOAD_16BIT"/> |
| + <value value="12" name="A7XX_PERF_TP_FILTER_WORKLOAD_32BIT"/> |
| + <value value="13" name="A7XX_PERF_TP_QUADS_RECEIVED"/> |
| + <value value="14" name="A7XX_PERF_TP_QUADS_OFFSET"/> |
| + <value value="15" name="A7XX_PERF_TP_QUADS_SHADOW"/> |
| + <value value="16" name="A7XX_PERF_TP_QUADS_ARRAY"/> |
| + <value value="17" name="A7XX_PERF_TP_QUADS_GRADIENT"/> |
| + <value value="18" name="A7XX_PERF_TP_QUADS_1D"/> |
| + <value value="19" name="A7XX_PERF_TP_QUADS_2D"/> |
| + <value value="20" name="A7XX_PERF_TP_QUADS_BUFFER"/> |
| + <value value="21" name="A7XX_PERF_TP_QUADS_3D"/> |
| + <value value="22" name="A7XX_PERF_TP_QUADS_CUBE"/> |
| + <value value="23" name="A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED"/> |
| + <value value="24" name="A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS"/> |
| + <value value="25" name="A7XX_PERF_TP_OUTPUT_PIXELS_POINT"/> |
| + <value value="26" name="A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR"/> |
| + <value value="27" name="A7XX_PERF_TP_OUTPUT_PIXELS_MIP"/> |
| + <value value="28" name="A7XX_PERF_TP_OUTPUT_PIXELS_ANISO"/> |
| + <value value="29" name="A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> |
| + <value value="30" name="A7XX_PERF_TP_FLAG_CACHE_REQUESTS"/> |
| + <value value="31" name="A7XX_PERF_TP_FLAG_CACHE_MISSES"/> |
| + <value value="32" name="A7XX_PERF_TP_L1_5_L2_REQUESTS"/> |
| + <value value="33" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS"/> |
| + <value value="34" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT"/> |
| + <value value="35" name="A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> |
| + <value value="36" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> |
| + <value value="37" name="A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> |
| + <value value="38" name="A7XX_PERF_TP_TPA2TPC_TRANS"/> |
| + <value value="39" name="A7XX_PERF_TP_L1_MISSES_ASTC_1TILE"/> |
| + <value value="40" name="A7XX_PERF_TP_L1_MISSES_ASTC_2TILE"/> |
| + <value value="41" name="A7XX_PERF_TP_L1_MISSES_ASTC_4TILE"/> |
| + <value value="42" name="A7XX_PERF_TP_L1_5_COMPRESS_REQS"/> |
| + <value value="43" name="A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS"/> |
| + <value value="44" name="A7XX_PERF_TP_L1_BANK_CONFLICT"/> |
| + <value value="45" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> |
| + <value value="46" name="A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS"/> |
| + <value value="47" name="A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> |
| + <value value="48" name="A7XX_PERF_TP_FRONTEND_WORKING_CYCLES"/> |
| + <value value="49" name="A7XX_PERF_TP_L1_TAG_WORKING_CYCLES"/> |
| + <value value="50" name="A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> |
| + <value value="51" name="A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> |
| + <value value="52" name="A7XX_PERF_TP_BACKEND_WORKING_CYCLES"/> |
| + <value value="53" name="A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> |
| + <value value="54" name="A7XX_PERF_TP_STARVE_CYCLES_SP"/> |
| + <value value="55" name="A7XX_PERF_TP_STARVE_CYCLES_UCHE"/> |
| + <value value="56" name="A7XX_PERF_TP_STALL_CYCLES_UFC"/> |
| + <value value="57" name="A7XX_PERF_TP_FORMAT_DECOMP"/> |
| + <value value="58" name="A7XX_PERF_TP_FILTER_POINT_FP16"/> |
| + <value value="59" name="A7XX_PERF_TP_FILTER_POINT_FP32"/> |
| + <value value="60" name="A7XX_PERF_TP_LATENCY_FIFO_FULL"/> |
| + <value value="61" name="A7XX_PERF_TP_RESERVED_61"/> |
| + <value value="62" name="A7XX_PERF_TP_RESERVED_62"/> |
| + <value value="63" name="A7XX_PERF_TP_RESERVED_63"/> |
| + <value value="64" name="A7XX_PERF_TP_RESERVED_64"/> |
| + <value value="65" name="A7XX_PERF_TP_RESERVED_65"/> |
| + <value value="66" name="A7XX_PERF_TP_RESERVED_66"/> |
| + <value value="67" name="A7XX_PERF_TP_RESERVED_67"/> |
| + <value value="68" name="A7XX_PERF_TP_RESERVED_68"/> |
| + <value value="69" name="A7XX_PERF_TP_RESERVED_69"/> |
| + <value value="70" name="A7XX_PERF_TP_RESERVED_70"/> |
| + <value value="71" name="A7XX_PERF_TP_RESERVED_71"/> |
| + <value value="72" name="A7XX_PERF_TP_RESERVED_72"/> |
| + <value value="73" name="A7XX_PERF_TP_RESERVED_73"/> |
| + <value value="74" name="A7XX_PERF_TP_RESERVED_74"/> |
| + <value value="75" name="A7XX_PERF_TP_RESERVED_75"/> |
| + <value value="76" name="A7XX_PERF_TP_RESERVED_76"/> |
| + <value value="77" name="A7XX_PERF_TP_RESERVED_77"/> |
| + <value value="78" name="A7XX_PERF_TP_RESERVED_78"/> |
| + <value value="79" name="A7XX_PERF_TP_RESERVED_79"/> |
| + <value value="80" name="A7XX_PERF_TP_RESERVED_80"/> |
| + <value value="81" name="A7XX_PERF_TP_RESERVED_81"/> |
| + <value value="82" name="A7XX_PERF_TP_RESERVED_82"/> |
| + <value value="83" name="A7XX_PERF_TP_RESERVED_83"/> |
| + <value value="84" name="A7XX_PERF_TP_RESERVED_84"/> |
| + <value value="85" name="A7XX_PERF_TP_RESERVED_85"/> |
| + <value value="86" name="A7XX_PERF_TP_RESERVED_86"/> |
| + <value value="87" name="A7XX_PERF_TP_RESERVED_87"/> |
| + <value value="88" name="A7XX_PERF_TP_RESERVED_88"/> |
| + <value value="89" name="A7XX_PERF_TP_RESERVED_89"/> |
| + <value value="90" name="A7XX_PERF_TP_RESERVED_90"/> |
| + <value value="91" name="A7XX_PERF_TP_RESERVED_91"/> |
| + <value value="92" name="A7XX_PERF_TP_RESERVED_92"/> |
| + <value value="93" name="A7XX_PERF_TP_RESERVED_93"/> |
| + <value value="94" name="A7XX_PERF_TP_RESERVED_94"/> |
| + <value value="95" name="A7XX_PERF_TP_RESERVED_95"/> |
| + <value value="96" name="A7XX_PERF_TP_RESERVED_96"/> |
| + <value value="97" name="A7XX_PERF_TP_RESERVED_97"/> |
| + <value value="98" name="A7XX_PERF_TP_RESERVED_98"/> |
| + <value value="99" name="A7XX_PERF_TP_RESERVED_99"/> |
| + <value value="100" name="A7XX_PERF_TP_RESERVED_100"/> |
| + <value value="101" name="A7XX_PERF_TP_RESERVED_101"/> |
| + <value value="102" name="A7XX_PERF_TP_RESERVED_102"/> |
| + <value value="103" name="A7XX_PERF_TP_RESERVED_103"/> |
| + <value value="104" name="A7XX_PERF_TP_RESERVED_104"/> |
| + <value value="105" name="A7XX_PERF_TP_RESERVED_105"/> |
| + <value value="106" name="A7XX_PERF_TP_RESERVED_106"/> |
| + <value value="107" name="A7XX_PERF_TP_RESERVED_107"/> |
| + <value value="108" name="A7XX_PERF_TP_RESERVED_108"/> |
| + <value value="109" name="A7XX_PERF_TP_RESERVED_109"/> |
| + <value value="110" name="A7XX_PERF_TP_RESERVED_110"/> |
| + <value value="111" name="A7XX_PERF_TP_RESERVED_111"/> |
| + <value value="112" name="A7XX_PERF_TP_RESERVED_112"/> |
| + <value value="113" name="A7XX_PERF_TP_RESERVED_113"/> |
| + <value value="114" name="A7XX_PERF_TP_RESERVED_114"/> |
| + <value value="115" name="A7XX_PERF_TP_RESERVED_115"/> |
| + <value value="116" name="A7XX_PERF_TP_RESERVED_116"/> |
| + <value value="117" name="A7XX_PERF_TP_RESERVED_117"/> |
| + <value value="118" name="A7XX_PERF_TP_RESERVED_118"/> |
| + <value value="119" name="A7XX_PERF_TP_RESERVED_119"/> |
| + <value value="120" name="A7XX_PERF_TP_RESERVED_120"/> |
| + <value value="121" name="A7XX_PERF_TP_RESERVED_121"/> |
| + <value value="122" name="A7XX_PERF_TP_RESERVED_122"/> |
| + <value value="123" name="A7XX_PERF_TP_RESERVED_123"/> |
| + <value value="124" name="A7XX_PERF_TP_RESERVED_124"/> |
| + <value value="125" name="A7XX_PERF_TP_RESERVED_125"/> |
| + <value value="126" name="A7XX_PERF_TP_RESERVED_126"/> |
| + <value value="127" name="A7XX_PERF_TP_RESERVED_127"/> |
| + <value value="128" name="A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR"/> |
| + <value value="129" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16"/> |
| + <value value="130" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16"/> |
| + <value value="131" name="A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32"/> |
| + <value value="132" name="A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32"/> |
| +</enum> |
| + |
| +<enum name="a7xx_sp_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_SP_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_SP_ALU_WORKING_CYCLES"/> |
| + <value value="2" name="A7XX_PERF_SP_EFU_WORKING_CYCLES"/> |
| + <value value="3" name="A7XX_PERF_SP_STALL_CYCLES_VPC"/> |
| + <value value="4" name="A7XX_PERF_SP_STALL_CYCLES_TP"/> |
| + <value value="5" name="A7XX_PERF_SP_STALL_CYCLES_UCHE"/> |
| + <value value="6" name="A7XX_PERF_SP_STALL_CYCLES_RB"/> |
| + <value value="7" name="A7XX_PERF_SP_NON_EXECUTION_CYCLES"/> |
| + <value value="8" name="A7XX_PERF_SP_WAVE_CONTEXTS"/> |
| + <value value="9" name="A7XX_PERF_SP_WAVE_CONTEXT_CYCLES"/> |
| + <value value="10" name="A7XX_PERF_SP_STAGE_WAVE_CYCLES"/> |
| + <value value="11" name="A7XX_PERF_SP_STAGE_WAVE_SAMPLES"/> |
| + <value value="12" name="A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES"/> |
| + <value value="13" name="A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES"/> |
| + <value value="14" name="A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES"/> |
| + <value value="15" name="A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES"/> |
| + <value value="16" name="A7XX_PERF_SP_WAVE_CTRL_CYCLES"/> |
| + <value value="17" name="A7XX_PERF_SP_WAVE_LOAD_CYCLES"/> |
| + <value value="18" name="A7XX_PERF_SP_WAVE_EMIT_CYCLES"/> |
| + <value value="19" name="A7XX_PERF_SP_WAVE_NOP_CYCLES"/> |
| + <value value="20" name="A7XX_PERF_SP_WAVE_WAIT_CYCLES"/> |
| + <value value="21" name="A7XX_PERF_SP_WAVE_FETCH_CYCLES"/> |
| + <value value="22" name="A7XX_PERF_SP_WAVE_IDLE_CYCLES"/> |
| + <value value="23" name="A7XX_PERF_SP_WAVE_END_CYCLES"/> |
| + <value value="24" name="A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES"/> |
| + <value value="25" name="A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> |
| + <value value="26" name="A7XX_PERF_SP_WAVE_JOIN_CYCLES"/> |
| + <value value="27" name="A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS"/> |
| + <value value="28" name="A7XX_PERF_SP_LM_STORE_INSTRUCTIONS"/> |
| + <value value="29" name="A7XX_PERF_SP_LM_ATOMICS"/> |
| + <value value="30" name="A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS"/> |
| + <value value="31" name="A7XX_PERF_SP_GM_STORE_INSTRUCTIONS"/> |
| + <value value="32" name="A7XX_PERF_SP_GM_ATOMICS"/> |
| + <value value="33" name="A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> |
| + <value value="34" name="A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> |
| + <value value="35" name="A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| + <value value="36" name="A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| + <value value="37" name="A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> |
| + <value value="38" name="A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> |
| + <value value="39" name="A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> |
| + <value value="40" name="A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> |
| + <value value="41" name="A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> |
| + <value value="42" name="A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> |
| + <value value="43" name="A7XX_PERF_SP_VS_INSTRUCTIONS"/> |
| + <value value="44" name="A7XX_PERF_SP_FS_INSTRUCTIONS"/> |
| + <value value="45" name="A7XX_PERF_SP_ADDR_LOCK_COUNT"/> |
| + <value value="46" name="A7XX_PERF_SP_UCHE_READ_TRANS"/> |
| + <value value="47" name="A7XX_PERF_SP_UCHE_WRITE_TRANS"/> |
| + <value value="48" name="A7XX_PERF_SP_EXPORT_VPC_TRANS"/> |
| + <value value="49" name="A7XX_PERF_SP_EXPORT_RB_TRANS"/> |
| + <value value="50" name="A7XX_PERF_SP_PIXELS_KILLED"/> |
| + <value value="51" name="A7XX_PERF_SP_ICL1_REQUESTS"/> |
| + <value value="52" name="A7XX_PERF_SP_ICL1_MISSES"/> |
| + <value value="53" name="A7XX_PERF_SP_HS_INSTRUCTIONS"/> |
| + <value value="54" name="A7XX_PERF_SP_DS_INSTRUCTIONS"/> |
| + <value value="55" name="A7XX_PERF_SP_GS_INSTRUCTIONS"/> |
| + <value value="56" name="A7XX_PERF_SP_CS_INSTRUCTIONS"/> |
| + <value value="57" name="A7XX_PERF_SP_GPR_READ"/> |
| + <value value="58" name="A7XX_PERF_SP_GPR_WRITE"/> |
| + <value value="59" name="A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| + <value value="60" name="A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> |
| + <value value="61" name="A7XX_PERF_SP_LM_BANK_CONFLICTS"/> |
| + <value value="62" name="A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> |
| + <value value="63" name="A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> |
| + <value value="64" name="A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> |
| + <value value="65" name="A7XX_PERF_SP_LM_WORKING_CYCLES"/> |
| + <value value="66" name="A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES"/> |
| + <value value="67" name="A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES"/> |
| + <value value="68" name="A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> |
| + <value value="69" name="A7XX_PERF_SP_STARVE_CYCLES_HLSQ"/> |
| + <value value="70" name="A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES"/> |
| + <value value="71" name="A7XX_PERF_SP_WORKING_EU"/> |
| + <value value="72" name="A7XX_PERF_SP_ANY_EU_WORKING"/> |
| + <value value="73" name="A7XX_PERF_SP_WORKING_EU_FS_STAGE"/> |
| + <value value="74" name="A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE"/> |
| + <value value="75" name="A7XX_PERF_SP_WORKING_EU_VS_STAGE"/> |
| + <value value="76" name="A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE"/> |
| + <value value="77" name="A7XX_PERF_SP_WORKING_EU_CS_STAGE"/> |
| + <value value="78" name="A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE"/> |
| + <value value="79" name="A7XX_PERF_SP_GPR_READ_PREFETCH"/> |
| + <value value="80" name="A7XX_PERF_SP_GPR_READ_CONFLICT"/> |
| + <value value="81" name="A7XX_PERF_SP_GPR_WRITE_CONFLICT"/> |
| + <value value="82" name="A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES"/> |
| + <value value="83" name="A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> |
| + <value value="84" name="A7XX_PERF_SP_EXECUTABLE_WAVES"/> |
| + <value value="85" name="A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES"/> |
| + <value value="86" name="A7XX_PERF_SP_WORKING_EU_LPAC"/> |
| + <value value="87" name="A7XX_PERF_SP_BYPASS_BUSY_CYCLES"/> |
| + <value value="88" name="A7XX_PERF_SP_ANY_EU_WORKING_LPAC"/> |
| + <value value="89" name="A7XX_PERF_SP_WAVE_ALU_CYCLES"/> |
| + <value value="90" name="A7XX_PERF_SP_WAVE_EFU_CYCLES"/> |
| + <value value="91" name="A7XX_PERF_SP_WAVE_INT_CYCLES"/> |
| + <value value="92" name="A7XX_PERF_SP_WAVE_CSP_CYCLES"/> |
| + <value value="93" name="A7XX_PERF_SP_EWAVE_CONTEXTS"/> |
| + <value value="94" name="A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES"/> |
| + <value value="95" name="A7XX_PERF_SP_LPAC_BUSY_CYCLES"/> |
| + <value value="96" name="A7XX_PERF_SP_LPAC_INSTRUCTIONS"/> |
| + <value value="97" name="A7XX_PERF_SP_FS_STAGE_1X_WAVES"/> |
| + <value value="98" name="A7XX_PERF_SP_FS_STAGE_2X_WAVES"/> |
| + <value value="99" name="A7XX_PERF_SP_QUADS"/> |
| + <value value="100" name="A7XX_PERF_SP_CS_INVOCATIONS"/> |
| + <value value="101" name="A7XX_PERF_SP_PIXELS"/> |
| + <value value="102" name="A7XX_PERF_SP_LPAC_DRAWCALLS"/> |
| + <value value="103" name="A7XX_PERF_SP_PI_WORKING_CYCLES"/> |
| + <value value="104" name="A7XX_PERF_SP_WAVE_INPUT_CYCLES"/> |
| + <value value="105" name="A7XX_PERF_SP_WAVE_OUTPUT_CYCLES"/> |
| + <value value="106" name="A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES"/> |
| + <value value="107" name="A7XX_PERF_SP_WAVE_HWAVE_SYNC"/> |
| + <value value="108" name="A7XX_PERF_SP_OUTPUT_3D_PIXELS"/> |
| + <value value="109" name="A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS"/> |
| + <value value="110" name="A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS"/> |
| + <value value="111" name="A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS"/> |
| + <value value="112" name="A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS"/> |
| + <value value="113" name="A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS"/> |
| + <value value="114" name="A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS"/> |
| + <value value="115" name="A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS"/> |
| + <value value="116" name="A7XX_PERF_SP_ALU_GPR_READ_CYCLES"/> |
| + <value value="117" name="A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES"/> |
| + <value value="118" name="A7XX_PERF_SP_LM_FULL_CYCLES"/> |
| + <value value="119" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES"/> |
| + <value value="120" name="A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES"/> |
| + <value value="121" name="A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION"/> |
| + <value value="122" name="A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS"/> |
| + <value value="123" name="A7XX_PERF_SP_RBRT_KICKOFF_FIBERS"/> |
| + <value value="124" name="A7XX_PERF_SP_RBRT_KICKOFF_DQUADS"/> |
| + <value value="125" name="A7XX_PERF_SP_RTU_BUSY_CYCLES"/> |
| + <value value="126" name="A7XX_PERF_SP_RTU_L0_HITS"/> |
| + <value value="127" name="A7XX_PERF_SP_RTU_L0_MISSES"/> |
| + <value value="128" name="A7XX_PERF_SP_RTU_L0_HIT_ON_MISS"/> |
| + <value value="129" name="A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE"/> |
| + <value value="130" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE"/> |
| + <value value="131" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE"/> |
| + <value value="132" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE"/> |
| + <value value="133" name="A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA"/> |
| + <value value="134" name="A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT"/> |
| + <value value="135" name="A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT"/> |
| + <value value="136" name="A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE"/> |
| + <value value="137" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0"/> |
| + <value value="138" name="A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO"/> |
| + <value value="139" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES"/> |
| + <value value="140" name="A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES"/> |
| + <value value="141" name="A7XX_PERF_SP_STCHE_MISS_INC_VS"/> |
| + <value value="142" name="A7XX_PERF_SP_STCHE_MISS_INC_FS"/> |
| + <value value="143" name="A7XX_PERF_SP_STCHE_MISS_INC_BV"/> |
| + <value value="144" name="A7XX_PERF_SP_STCHE_MISS_INC_LPAC"/> |
| + <value value="145" name="A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS"/> |
| + <value value="146" name="A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS"/> |
| + <value value="147" name="A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS"/> |
| + <value value="148" name="A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS"/> |
| + <value value="149" name="A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS"/> |
| + <value value="150" name="A7XX_PERF_SP_SCH_STALL_CYCLES_RTU"/> |
| +</enum> |
| + |
| +<enum name="a7xx_rb_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_RB_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_RB_STALL_CYCLES_HLSQ"/> |
| + <value value="2" name="A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL"/> |
| + <value value="3" name="A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL"/> |
| + <value value="4" name="A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL"/> |
| + <value value="5" name="A7XX_PERF_RB_STARVE_CYCLES_SP"/> |
| + <value value="6" name="A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE"/> |
| + <value value="7" name="A7XX_PERF_RB_STARVE_CYCLES_CCU"/> |
| + <value value="8" name="A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE"/> |
| + <value value="9" name="A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE"/> |
| + <value value="10" name="A7XX_PERF_RB_Z_WORKLOAD"/> |
| + <value value="11" name="A7XX_PERF_RB_HLSQ_ACTIVE"/> |
| + <value value="12" name="A7XX_PERF_RB_Z_READ"/> |
| + <value value="13" name="A7XX_PERF_RB_Z_WRITE"/> |
| + <value value="14" name="A7XX_PERF_RB_C_READ"/> |
| + <value value="15" name="A7XX_PERF_RB_C_WRITE"/> |
| + <value value="16" name="A7XX_PERF_RB_TOTAL_PASS"/> |
| + <value value="17" name="A7XX_PERF_RB_Z_PASS"/> |
| + <value value="18" name="A7XX_PERF_RB_Z_FAIL"/> |
| + <value value="19" name="A7XX_PERF_RB_S_FAIL"/> |
| + <value value="20" name="A7XX_PERF_RB_BLENDED_FXP_COMPONENTS"/> |
| + <value value="21" name="A7XX_PERF_RB_BLENDED_FP16_COMPONENTS"/> |
| + <value value="22" name="A7XX_PERF_RB_PS_INVOCATIONS"/> |
| + <value value="23" name="A7XX_PERF_RB_2D_ALIVE_CYCLES"/> |
| + <value value="24" name="A7XX_PERF_RB_2D_STALL_CYCLES_A2D"/> |
| + <value value="25" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SRC"/> |
| + <value value="26" name="A7XX_PERF_RB_2D_STARVE_CYCLES_SP"/> |
| + <value value="27" name="A7XX_PERF_RB_2D_STARVE_CYCLES_DST"/> |
| + <value value="28" name="A7XX_PERF_RB_2D_VALID_PIXELS"/> |
| + <value value="29" name="A7XX_PERF_RB_3D_PIXELS"/> |
| + <value value="30" name="A7XX_PERF_RB_BLENDER_WORKING_CYCLES"/> |
| + <value value="31" name="A7XX_PERF_RB_ZPROC_WORKING_CYCLES"/> |
| + <value value="32" name="A7XX_PERF_RB_CPROC_WORKING_CYCLES"/> |
| + <value value="33" name="A7XX_PERF_RB_SAMPLER_WORKING_CYCLES"/> |
| + <value value="34" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> |
| + <value value="35" name="A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> |
| + <value value="36" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> |
| + <value value="37" name="A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> |
| + <value value="38" name="A7XX_PERF_RB_STALL_CYCLES_VPC"/> |
| + <value value="39" name="A7XX_PERF_RB_2D_INPUT_TRANS"/> |
| + <value value="40" name="A7XX_PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> |
| + <value value="41" name="A7XX_PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> |
| + <value value="42" name="A7XX_PERF_RB_BLENDED_FP32_COMPONENTS"/> |
| + <value value="43" name="A7XX_PERF_RB_COLOR_PIX_TILES"/> |
| + <value value="44" name="A7XX_PERF_RB_STALL_CYCLES_CCU"/> |
| + <value value="45" name="A7XX_PERF_RB_EARLY_Z_ARB3_GRANT"/> |
| + <value value="46" name="A7XX_PERF_RB_LATE_Z_ARB3_GRANT"/> |
| + <value value="47" name="A7XX_PERF_RB_EARLY_Z_SKIP_GRANT"/> |
| + <value value="48" name="A7XX_PERF_RB_VRS_1x1_QUADS"/> |
| + <value value="49" name="A7XX_PERF_RB_VRS_2x1_QUADS"/> |
| + <value value="50" name="A7XX_PERF_RB_VRS_1x2_QUADS"/> |
| + <value value="51" name="A7XX_PERF_RB_VRS_2x2_QUADS"/> |
| + <value value="52" name="A7XX_PERF_RB_VRS_4x2_QUADS"/> |
| + <value value="53" name="A7XX_PERF_RB_VRS_4x4_QUADS"/> |
| +</enum> |
| + |
| +<enum name="a7xx_vsc_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_VSC_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_VSC_WORKING_CYCLES"/> |
| + <value value="2" name="A7XX_PERF_VSC_STALL_CYCLES_UCHE"/> |
| + <value value="3" name="A7XX_PERF_VSC_EOT_NUM"/> |
| + <value value="4" name="A7XX_PERF_VSC_INPUT_TILES"/> |
| +</enum> |
| + |
| +<enum name="a7xx_ccu_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_CCU_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> |
| + <value value="2" name="A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> |
| + <value value="3" name="A7XX_PERF_CCU_DEPTH_BLOCKS"/> |
| + <value value="4" name="A7XX_PERF_CCU_COLOR_BLOCKS"/> |
| + <value value="5" name="A7XX_PERF_CCU_DEPTH_BLOCK_HIT"/> |
| + <value value="6" name="A7XX_PERF_CCU_COLOR_BLOCK_HIT"/> |
| + <value value="7" name="A7XX_PERF_CCU_PARTIAL_BLOCK_READ"/> |
| + <value value="8" name="A7XX_PERF_CCU_GMEM_READ"/> |
| + <value value="9" name="A7XX_PERF_CCU_GMEM_WRITE"/> |
| + <value value="10" name="A7XX_PERF_CCU_2D_RD_REQ"/> |
| + <value value="11" name="A7XX_PERF_CCU_2D_WR_REQ"/> |
| + <value value="12" name="A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT"/> |
| + <value value="13" name="A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT"/> |
| + <value value="14" name="A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED"/> |
| + <value value="15" name="A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED"/> |
| + <value value="16" name="A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT"/> |
| + <value value="17" name="A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT"/> |
| + <value value="18" name="A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER"/> |
| + <value value="19" name="A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER"/> |
| + <value value="20" name="A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ"/> |
| + <value value="21" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA"/> |
| + <value value="22" name="A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL"/> |
| +</enum> |
| + |
| +<enum name="a7xx_lrz_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_LRZ_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_LRZ_STARVE_CYCLES_RAS"/> |
| + <value value="2" name="A7XX_PERF_LRZ_STALL_CYCLES_RB"/> |
| + <value value="3" name="A7XX_PERF_LRZ_STALL_CYCLES_VSC"/> |
| + <value value="4" name="A7XX_PERF_LRZ_STALL_CYCLES_VPC"/> |
| + <value value="5" name="A7XX_PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> |
| + <value value="6" name="A7XX_PERF_LRZ_STALL_CYCLES_UCHE"/> |
| + <value value="7" name="A7XX_PERF_LRZ_LRZ_READ"/> |
| + <value value="8" name="A7XX_PERF_LRZ_LRZ_WRITE"/> |
| + <value value="9" name="A7XX_PERF_LRZ_READ_LATENCY"/> |
| + <value value="10" name="A7XX_PERF_LRZ_MERGE_CACHE_UPDATING"/> |
| + <value value="11" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> |
| + <value value="12" name="A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ"/> |
| + <value value="13" name="A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> |
| + <value value="14" name="A7XX_PERF_LRZ_FULL_8X8_TILES"/> |
| + <value value="15" name="A7XX_PERF_LRZ_PARTIAL_8X8_TILES"/> |
| + <value value="16" name="A7XX_PERF_LRZ_TILE_KILLED"/> |
| + <value value="17" name="A7XX_PERF_LRZ_TOTAL_PIXEL"/> |
| + <value value="18" name="A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> |
| + <value value="19" name="A7XX_PERF_LRZ_FEEDBACK_ACCEPT"/> |
| + <value value="20" name="A7XX_PERF_LRZ_FEEDBACK_DISCARD"/> |
| + <value value="21" name="A7XX_PERF_LRZ_FEEDBACK_STALL"/> |
| + <value value="22" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> |
| + <value value="23" name="A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> |
| + <value value="24" name="A7XX_PERF_LRZ_RAS_MASK_TRANS"/> |
| + <value value="25" name="A7XX_PERF_LRZ_STALL_CYCLES_MVC"/> |
| + <value value="26" name="A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS"/> |
| + <value value="27" name="A7XX_PERF_LRZ_TILE_KILLED_BY_Z"/> |
| +</enum> |
| + |
| +<enum name="a7xx_cmp_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB"/> |
| + <value value="1" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> |
| + <value value="2" name="A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> |
| + <value value="3" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> |
| + <value value="4" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> |
| + <value value="5" name="A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST"/> |
| + <value value="6" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> |
| + <value value="7" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA"/> |
| + <value value="8" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA"/> |
| + <value value="9" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> |
| + <value value="10" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> |
| + <value value="11" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> |
| + <value value="12" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> |
| + <value value="13" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> |
| + <value value="14" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> |
| + <value value="15" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> |
| + <value value="16" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> |
| + <value value="17" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> |
| + <value value="18" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> |
| + <value value="19" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> |
| + <value value="20" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> |
| + <value value="21" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> |
| + <value value="22" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> |
| + <value value="23" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> |
| + <value value="24" name="A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> |
| + <value value="25" name="A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> |
| + <value value="26" name="A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> |
| + <value value="27" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> |
| + <value value="28" name="A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> |
| + <value value="29" name="A7XX_PERF_CMPDECMP_RESOLVE_EVENTS"/> |
| + <value value="30" name="A7XX_PERF_CMPDECMP_CONCURRENT_RESOLVE_EVENTS"/> |
| + <value value="31" name="A7XX_PERF_CMPDECMP_DROPPED_CLEAR_EVENTS"/> |
| + <value value="32" name="A7XX_PERF_CMPDECMP_ST_BLOCKS_CONCURRENT"/> |
| + <value value="33" name="A7XX_PERF_CMPDECMP_LRZ_ST_BLOCKS_CONCURRENT"/> |
| + <value value="34" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT"/> |
| + <value value="35" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT"/> |
| + <value value="36" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT"/> |
| + <value value="37" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT"/> |
| + <value value="38" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT"/> |
| + <value value="39" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT"/> |
| + <value value="40" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT"/> |
| + <value value="41" name="A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT"/> |
| + <value value="42" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT"/> |
| + <value value="43" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT"/> |
| + <value value="44" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT"/> |
| + <value value="45" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT"/> |
| + <value value="46" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT"/> |
| + <value value="47" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT"/> |
| + <value value="48" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT"/> |
| + <value value="49" name="A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT"/> |
| +</enum> |
| + |
| +<enum name="a7xx_gbif_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_GBIF_RESERVED_0"/> |
| + <value value="1" name="A7XX_PERF_GBIF_RESERVED_1"/> |
| + <value value="2" name="A7XX_PERF_GBIF_RESERVED_2"/> |
| + <value value="3" name="A7XX_PERF_GBIF_RESERVED_3"/> |
| + <value value="4" name="A7XX_PERF_GBIF_RESERVED_4"/> |
| + <value value="5" name="A7XX_PERF_GBIF_RESERVED_5"/> |
| + <value value="6" name="A7XX_PERF_GBIF_RESERVED_6"/> |
| + <value value="7" name="A7XX_PERF_GBIF_RESERVED_7"/> |
| + <value value="8" name="A7XX_PERF_GBIF_RESERVED_8"/> |
| + <value value="9" name="A7XX_PERF_GBIF_RESERVED_9"/> |
| + <value value="10" name="A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL"/> |
| + <value value="11" name="A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL"/> |
| + <value value="12" name="A7XX_PERF_GBIF_RESERVED_12"/> |
| + <value value="13" name="A7XX_PERF_GBIF_RESERVED_13"/> |
| + <value value="14" name="A7XX_PERF_GBIF_RESERVED_14"/> |
| + <value value="15" name="A7XX_PERF_GBIF_RESERVED_15"/> |
| + <value value="16" name="A7XX_PERF_GBIF_RESERVED_16"/> |
| + <value value="17" name="A7XX_PERF_GBIF_RESERVED_17"/> |
| + <value value="18" name="A7XX_PERF_GBIF_RESERVED_18"/> |
| + <value value="19" name="A7XX_PERF_GBIF_RESERVED_19"/> |
| + <value value="20" name="A7XX_PERF_GBIF_RESERVED_20"/> |
| + <value value="21" name="A7XX_PERF_GBIF_RESERVED_21"/> |
| + <value value="22" name="A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL"/> |
| + <value value="23" name="A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL"/> |
| + <value value="24" name="A7XX_PERF_GBIF_RESERVED_24"/> |
| + <value value="25" name="A7XX_PERF_GBIF_RESERVED_25"/> |
| + <value value="26" name="A7XX_PERF_GBIF_RESERVED_26"/> |
| + <value value="27" name="A7XX_PERF_GBIF_RESERVED_27"/> |
| + <value value="28" name="A7XX_PERF_GBIF_RESERVED_28"/> |
| + <value value="29" name="A7XX_PERF_GBIF_RESERVED_29"/> |
| + <value value="30" name="A7XX_PERF_GBIF_RESERVED_30"/> |
| + <value value="31" name="A7XX_PERF_GBIF_RESERVED_31"/> |
| + <value value="32" name="A7XX_PERF_GBIF_RESERVED_32"/> |
| + <value value="33" name="A7XX_PERF_GBIF_RESERVED_33"/> |
| + <value value="34" name="A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL"/> |
| + <value value="35" name="A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL"/> |
| + <value value="36" name="A7XX_PERF_GBIF_RESERVED_36"/> |
| + <value value="37" name="A7XX_PERF_GBIF_RESERVED_37"/> |
| + <value value="38" name="A7XX_PERF_GBIF_RESERVED_38"/> |
| + <value value="39" name="A7XX_PERF_GBIF_RESERVED_39"/> |
| + <value value="40" name="A7XX_PERF_GBIF_RESERVED_40"/> |
| + <value value="41" name="A7XX_PERF_GBIF_RESERVED_41"/> |
| + <value value="42" name="A7XX_PERF_GBIF_RESERVED_42"/> |
| + <value value="43" name="A7XX_PERF_GBIF_RESERVED_43"/> |
| + <value value="44" name="A7XX_PERF_GBIF_RESERVED_44"/> |
| + <value value="45" name="A7XX_PERF_GBIF_RESERVED_45"/> |
| + <value value="46" name="A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL"/> |
| + <value value="47" name="A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL"/> |
| + <value value="48" name="A7XX_PERF_GBIF_RESERVED_48"/> |
| + <value value="49" name="A7XX_PERF_GBIF_RESERVED_49"/> |
| + <value value="50" name="A7XX_PERF_GBIF_RESERVED_50"/> |
| + <value value="51" name="A7XX_PERF_GBIF_RESERVED_51"/> |
| + <value value="52" name="A7XX_PERF_GBIF_RESERVED_52"/> |
| + <value value="53" name="A7XX_PERF_GBIF_RESERVED_53"/> |
| + <value value="54" name="A7XX_PERF_GBIF_RESERVED_54"/> |
| + <value value="55" name="A7XX_PERF_GBIF_RESERVED_55"/> |
| + <value value="56" name="A7XX_PERF_GBIF_RESERVED_56"/> |
| + <value value="57" name="A7XX_PERF_GBIF_RESERVED_57"/> |
| + <value value="58" name="A7XX_PERF_GBIF_RESERVED_58"/> |
| + <value value="59" name="A7XX_PERF_GBIF_RESERVED_59"/> |
| + <value value="60" name="A7XX_PERF_GBIF_RESERVED_60"/> |
| + <value value="61" name="A7XX_PERF_GBIF_RESERVED_61"/> |
| + <value value="62" name="A7XX_PERF_GBIF_RESERVED_62"/> |
| + <value value="63" name="A7XX_PERF_GBIF_RESERVED_63"/> |
| + <value value="64" name="A7XX_PERF_GBIF_RESERVED_64"/> |
| + <value value="65" name="A7XX_PERF_GBIF_RESERVED_65"/> |
| + <value value="66" name="A7XX_PERF_GBIF_RESERVED_66"/> |
| + <value value="67" name="A7XX_PERF_GBIF_RESERVED_67"/> |
| + <value value="68" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL"/> |
| + <value value="69" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL"/> |
| + <value value="70" name="A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL"/> |
| + <value value="71" name="A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL"/> |
| + <value value="72" name="A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF"/> |
| + <value value="73" name="A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF"/> |
| + <value value="74" name="A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF"/> |
| + <value value="75" name="A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF"/> |
| + <value value="76" name="A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF"/> |
| + <value value="77" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF"/> |
| + <value value="78" name="A7XX_PERF_GBIF_AXI_ALL_READ_BEATS"/> |
| + <value value="79" name="A7XX_PERF_GBIF_AXI_ALL_WRITE_BEATS"/> |
| + <value value="80" name="A7XX_PERF_GBIF_AXI_ALL_BEATS"/> |
| +</enum> |
| + |
| +<enum name="a7xx_ufc_perfcounter_select"> |
| + <value value="0" name="A7XX_PERF_UFC_BUSY_CYCLES"/> |
| + <value value="1" name="A7XX_PERF_UFC_READ_DATA_VBIF"/> |
| + <value value="2" name="A7XX_PERF_UFC_WRITE_DATA_VBIF"/> |
| + <value value="3" name="A7XX_PERF_UFC_READ_REQUEST_VBIF"/> |
| + <value value="4" name="A7XX_PERF_UFC_WRITE_REQUEST_VBIF"/> |
| + <value value="5" name="A7XX_PERF_UFC_LRZ_FILTER_HIT"/> |
| + <value value="6" name="A7XX_PERF_UFC_LRZ_FILTER_MISS"/> |
| + <value value="7" name="A7XX_PERF_UFC_CRE_FILTER_HIT"/> |
| + <value value="8" name="A7XX_PERF_UFC_CRE_FILTER_MISS"/> |
| + <value value="9" name="A7XX_PERF_UFC_SP_FILTER_HIT"/> |
| + <value value="10" name="A7XX_PERF_UFC_SP_FILTER_MISS"/> |
| + <value value="11" name="A7XX_PERF_UFC_SP_REQUESTS"/> |
| + <value value="12" name="A7XX_PERF_UFC_TP_FILTER_HIT"/> |
| + <value value="13" name="A7XX_PERF_UFC_TP_FILTER_MISS"/> |
| + <value value="14" name="A7XX_PERF_UFC_TP_REQUESTS"/> |
| + <value value="15" name="A7XX_PERF_UFC_MAIN_HIT_LRZ_PREFETCH"/> |
| + <value value="16" name="A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH"/> |
| + <value value="17" name="A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH"/> |
| + <value value="18" name="A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH"/> |
| + <value value="19" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_READ"/> |
| + <value value="20" name="A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE"/> |
| + <value value="21" name="A7XX_PERF_UFC_MAIN_MISS_LRZ_PREFETCH"/> |
| + <value value="22" name="A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH"/> |
| + <value value="23" name="A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH"/> |
| + <value value="24" name="A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH"/> |
| + <value value="25" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_READ"/> |
| + <value value="26" name="A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE"/> |
| + <value value="27" name="A7XX_PERF_UFC_UBWC_READ_UFC_TRANS"/> |
| + <value value="28" name="A7XX_PERF_UFC_UBWC_WRITE_UFC_TRANS"/> |
| + <value value="29" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD"/> |
| + <value value="30" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA"/> |
| + <value value="31" name="A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA"/> |
| + <value value="32" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG"/> |
| + <value value="33" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN"/> |
| + <value value="34" name="A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT"/> |
| + <value value="35" name="A7XX_PERF_UFC_LRZ_PREFETCH_STALLED_CYCLES"/> |
| + <value value="36" name="A7XX_PERF_UFC_CRE_PREFETCH_STALLED_CYCLES"/> |
| + <value value="37" name="A7XX_PERF_UFC_SPTP_PREFETCH_STALLED_CYCLES"/> |
| + <value value="38" name="A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES"/> |
| + <value value="39" name="A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES"/> |
| + <value value="40" name="A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES"/> |
| + <value value="41" name="A7XX_PERF_UFC_EVICTION_STALLED_CYCLES"/> |
| + <value value="42" name="A7XX_PERF_UFC_LOCK_STALLED_CYCLES"/> |
| + <value value="43" name="A7XX_PERF_UFC_MISS_LATENCY_CYCLES"/> |
| + <value value="44" name="A7XX_PERF_UFC_MISS_LATENCY_SAMPLES"/> |
| + <value value="45" name="A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES"/> |
| + <value value="46" name="A7XX_PERF_UFC_TP_HINT_TAG_MISS"/> |
| + <value value="47" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_RDY"/> |
| + <value value="48" name="A7XX_PERF_UFC_TP_HINT_TAG_HIT_NRDY"/> |
| + <value value="49" name="A7XX_PERF_UFC_TP_HINT_IS_FCLEAR"/> |
| + <value value="50" name="A7XX_PERF_UFC_TP_HINT_IS_ALPHA0"/> |
| + <value value="51" name="A7XX_PERF_UFC_SP_L1_FILTER_HIT"/> |
| + <value value="52" name="A7XX_PERF_UFC_SP_L1_FILTER_MISS"/> |
| + <value value="53" name="A7XX_PERF_UFC_SP_L1_FILTER_REQUESTS"/> |
| + <value value="54" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_RDY"/> |
| + <value value="55" name="A7XX_PERF_UFC_TP_L1_TAG_HIT_NRDY"/> |
| + <value value="56" name="A7XX_PERF_UFC_TP_L1_TAG_MISS"/> |
| + <value value="57" name="A7XX_PERF_UFC_TP_L1_FILTER_REQUESTS"/> |
| +</enum> |
| + |
| +</database> |
| diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml |
| index 462713401622..7abc08635495 100644 |
| --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml |
| +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml |
| @@ -21,9 +21,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/> |
| <value name="VIZQUERY_END" value="8" variants="A2XX"/> |
| <value name="SC_WAIT_WC" value="9" variants="A2XX"/> |
| - <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/> |
| - <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/> |
| - <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/> |
| + <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/> |
| + <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/> |
| + <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/> |
| <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ --> |
| <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/> |
| <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/> |
| @@ -31,8 +31,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/> |
| <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/> |
| <doc> |
| - If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed |
| - sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main |
| + If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed |
| + sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main |
| memory, skipping UCHE. |
| </doc> |
| <value name="ZPASS_DONE" value="21"/> |
| @@ -97,6 +97,13 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| </doc> |
| <value name="BLIT" value="30" variants="A5XX-"/> |
| |
| + <doc> |
| + Flip between the primary and secondary LRZ buffers. This is used |
| + for concurrent binning, so that BV can write to one buffer while |
| + BR reads from the other. |
| + </doc> |
| + <value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/> |
| + |
| <doc> |
| Clears based on GRAS_LRZ_CNTL configuration, could clear |
| fast-clear buffer or LRZ direction. |
| @@ -114,6 +121,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> |
| <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/> |
| <value name="UNK_40" value="40" variants="A7XX"/> |
| + <value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/> |
| <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> |
| <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> |
| <value name="UNK_2C" value="44" variants="A5XX-"/> |
| @@ -372,7 +380,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/> |
| <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/> |
| <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> |
| - <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/> |
| + <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a" variants="A3XX-A5XX"/> |
| <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> |
| <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/> |
| <doc>Load a buffer with pre-fetch enabled</doc> |
| @@ -538,7 +546,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/> |
| <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/> |
| <!-- |
| - Note: For IBO state (Image/SSBOs) which have shared state across |
| + Note: For UAV state (Image/SSBOs) which have shared state across |
| shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for |
| compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are |
| interchangable. |
| @@ -567,7 +575,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/> |
| |
| <!-- TODO do these exist on A5xx? --> |
| - <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/> |
| + <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX-"/> |
| <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/> |
| <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/> |
| <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/> |
| @@ -650,6 +658,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> |
| |
| <doc>Reset various on-chip state used for synchronization</doc> |
| <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/> |
| + |
| + <doc>Invalidates the "CCHE" introduced on a740</doc> |
| + <value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/> |
| + |
| + <value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/> |
| </enum> |
| |
| |
| @@ -792,14 +805,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| <value name="SB6_GS_SHADER" value="0xb"/> |
| <value name="SB6_FS_SHADER" value="0xc"/> |
| <value name="SB6_CS_SHADER" value="0xd"/> |
| - <value name="SB6_IBO" value="0xe"/> |
| - <value name="SB6_CS_IBO" value="0xf"/> |
| + <value name="SB6_UAV" value="0xe"/> |
| + <value name="SB6_CS_UAV" value="0xf"/> |
| </enum> |
| <enum name="a6xx_state_type"> |
| <value name="ST6_SHADER" value="0"/> |
| <value name="ST6_CONSTANTS" value="1"/> |
| <value name="ST6_UBO" value="2"/> |
| - <value name="ST6_IBO" value="3"/> |
| + <value name="ST6_UAV" value="3"/> |
| </enum> |
| <enum name="a6xx_state_src"> |
| <value name="SS6_DIRECT" value="0"/> |
| @@ -1121,39 +1134,93 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| </reg32> |
| </domain> |
| |
| +<enum name="a7xx_abs_mask_mode"> |
| + <value name="ABS_MASK" value="0x1"/> |
| + <value name="NO_ABS_MASK" value="0x0"/> |
| +</enum> |
| + |
| <domain name="CP_SET_BIN_DATA5" width="32"> |
| <reg32 offset="0" name="0"> |
| + <bitfield name="VSC_MASK" low="0" high="15" type="hex"> |
| + <doc> |
| + A mask of bins, starting at VSC_N, whose |
| + visibility is OR'd together. A value of 0 is |
| + interpreted as 1 (i.e. just use VSC_N for |
| + visbility) for backwards compatibility. Only |
| + exists on a7xx. |
| + </doc> |
| + </bitfield> |
| <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> |
| <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> |
| <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> |
| <bitfield name="VSC_N" low="22" high="26" type="uint"/> |
| + <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"> |
| + <doc> |
| + If this field is 1, VSC_MASK and VSC_N are |
| + ignored and instead a new ordinal immediately |
| + after specifies the full 32-bit mask of bins |
| + to use. The mask is "absolute" instead of |
| + relative to VSC_N. |
| + </doc> |
| + </bitfield> |
| </reg32> |
| - <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> |
| - <reg32 offset="1" name="1"> |
| - <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> |
| - </reg32> |
| - <reg32 offset="2" name="2"> |
| - <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> |
| - </reg32> |
| - <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> |
| - <reg32 offset="3" name="3"> |
| - <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> |
| - </reg32> |
| - <reg32 offset="4" name="4"> |
| - <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> |
| - </reg32> |
| - <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> |
| - <reg32 offset="5" name="5"> |
| - <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> |
| - </reg32> |
| - <reg32 offset="6" name="6"> |
| - <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> |
| - </reg32> |
| - <!-- |
| - a7xx adds a few more addresses to the end of the pkt |
| - --> |
| - <reg64 offset="7" name="7"/> |
| - <reg64 offset="9" name="9"/> |
| + <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> |
| + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> |
| + <reg32 offset="1" name="1"> |
| + <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> |
| + </reg32> |
| + <reg32 offset="2" name="2"> |
| + <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> |
| + </reg32> |
| + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> |
| + <reg32 offset="3" name="3"> |
| + <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> |
| + </reg32> |
| + <reg32 offset="4" name="4"> |
| + <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> |
| + </reg32> |
| + <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> |
| + <reg32 offset="5" name="5"> |
| + <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> |
| + </reg32> |
| + <reg32 offset="6" name="6"> |
| + <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> |
| + </reg32> |
| + <!-- |
| + a7xx adds a few more addresses to the end of the pkt |
| + --> |
| + <reg64 offset="7" name="7"/> |
| + <reg64 offset="9" name="9"/> |
| + </stripe> |
| + <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> |
| + <reg32 offset="1" name="ABS_MASK"/> |
| + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> |
| + <reg32 offset="2" name="2"> |
| + <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> |
| + </reg32> |
| + <reg32 offset="3" name="3"> |
| + <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> |
| + </reg32> |
| + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> |
| + <reg32 offset="4" name="4"> |
| + <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> |
| + </reg32> |
| + <reg32 offset="5" name="5"> |
| + <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> |
| + </reg32> |
| + <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> |
| + <reg32 offset="6" name="6"> |
| + <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> |
| + </reg32> |
| + <reg32 offset="7" name="7"> |
| + <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> |
| + </reg32> |
| + <!-- |
| + a7xx adds a few more addresses to the end of the pkt |
| + --> |
| + <reg64 offset="8" name="8"/> |
| + <reg64 offset="10" name="10"/> |
| + </stripe> |
| </domain> |
| |
| <domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> |
| @@ -1164,23 +1231,42 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| stream is recorded. |
| </doc> |
| <reg32 offset="0" name="0"> |
| + <bitfield name="VSC_MASK" low="0" high="15" type="hex"/> |
| <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> |
| <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> |
| <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> |
| <bitfield name="VSC_N" low="22" high="26" type="uint"/> |
| + <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"/> |
| </reg32> |
| - <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> |
| - <reg32 offset="1" name="1"> |
| - <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> |
| - </reg32> |
| - <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> |
| - <reg32 offset="2" name="2"> |
| - <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> |
| - </reg32> |
| - <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> |
| - <reg32 offset="3" name="3"> |
| - <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> |
| - </reg32> |
| + <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> |
| + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> |
| + <reg32 offset="1" name="1"> |
| + <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> |
| + </reg32> |
| + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> |
| + <reg32 offset="2" name="2"> |
| + <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> |
| + </reg32> |
| + <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> |
| + <reg32 offset="3" name="3"> |
| + <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> |
| + </reg32> |
| + </stripe> |
| + <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> |
| + <reg32 offset="1" name="ABS_MASK"/> |
| + <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> |
| + <reg32 offset="2" name="2"> |
| + <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> |
| + </reg32> |
| + <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> |
| + <reg32 offset="3" name="3"> |
| + <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> |
| + </reg32> |
| + <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> |
| + <reg32 offset="4" name="4"> |
| + <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> |
| + </reg32> |
| + </stripe> |
| </domain> |
| |
| <domain name="CP_REG_RMW" width="32"> |
| @@ -1198,6 +1284,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| </doc> |
| <reg32 offset="0" name="0"> |
| <bitfield name="DST_REG" low="0" high="17" type="hex"/> |
| + <bitfield name="DST_SCRATCH" pos="19" type="boolean" varset="chip" variants="A7XX-"/> |
| + <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> |
| + <bitfield name="SKIP_WAIT_FOR_ME" pos="23" type="boolean" varset="chip" variants="A7XX-"/> |
| <bitfield name="ROTATE" low="24" high="28" type="uint"/> |
| <bitfield name="SRC1_ADD" pos="29" type="boolean"/> |
| <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> |
| @@ -1348,6 +1437,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| <bitfield name="SCRATCH" low="20" high="22" type="uint"/> |
| <!-- number of registers/dwords copied is CNT + 1. --> |
| <bitfield name="CNT" low="24" high="26" type="uint"/> |
| + <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> |
| + <bitfield name="SKIP_WAIT_FOR_ME" pos="27" type="boolean" varset="chip" variants="A7XX-"/> |
| </reg32> |
| </domain> |
| |
| @@ -1655,8 +1746,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/> |
| <!-- Write sample count at (iova + 16) --> |
| <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/> |
| - <!-- *(iova + 8) = *(iova + 16) - *iova --> |
| - <bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/> |
| + <!-- *(iova + 8) += *(iova + 16) - *iova --> |
| + <bitfield name="WRITE_ACCUM_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/> |
| |
| <!-- Next 4 flags are valid to set only when concurrent binning is enabled --> |
| <!-- Increment 16b BV counter. Valid only in BV pipe --> |
| @@ -1670,15 +1761,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/> |
| <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. --> |
| <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/> |
| + <bitfield name="IRQ" pos="31" type="boolean"/> |
| </reg32> |
| |
| <stripe varset="event_write_dst" variants="EV_DST_RAM"> |
| - <reg32 offset="1" name="1"> |
| - <bitfield name="ADDR_0_LO" low="0" high="31"/> |
| - </reg32> |
| - <reg32 offset="2" name="2"> |
| - <bitfield name="ADDR_0_HI" low="0" high="31"/> |
| - </reg32> |
| + <reg64 offset="1" name="1" type="waddress"/> |
| <reg32 offset="3" name="3"> |
| <bitfield name="PAYLOAD_0" low="0" high="31"/> |
| </reg32> |
| @@ -1773,13 +1860,23 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| |
| <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> |
| <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> |
| + <enum name="set_marker_mode"> |
| + <value value="0" name="SET_RENDER_MODE"/> |
| + <!-- IFPC - inter-frame power collapse --> |
| + <value value="1" name="SET_IFPC_MODE"/> |
| + </enum> |
| + <enum name="a6xx_ifpc_mode"> |
| + <value value="0" name="IFPC_ENABLE"/> |
| + <value value="1" name="IFPC_DISABLE"/> |
| + </enum> |
| <enum name="a6xx_marker"> |
| - <value value="1" name="RM6_BYPASS"/> |
| - <value value="2" name="RM6_BINNING"/> |
| - <value value="4" name="RM6_GMEM"/> |
| - <value value="5" name="RM6_ENDVIS"/> |
| - <value value="6" name="RM6_RESOLVE"/> |
| - <value value="7" name="RM6_YIELD"/> |
| + <value value="1" name="RM6_DIRECT_RENDER"/> |
| + <value value="2" name="RM6_BIN_VISIBILITY"/> |
| + <value value="3" name="RM6_BIN_DIRECT"/> |
| + <value value="4" name="RM6_BIN_RENDER_START"/> |
| + <value value="5" name="RM6_BIN_END_OF_DRAWS"/> |
| + <value value="6" name="RM6_BIN_RESOLVE"/> |
| + <value value="7" name="RM6_BIN_RENDER_END"/> |
| <value value="8" name="RM6_COMPUTE"/> |
| <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> |
| |
| @@ -1789,23 +1886,40 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| --> |
| <value value="0xd" name="RM6_IB1LIST_START"/> |
| <value value="0xe" name="RM6_IB1LIST_END"/> |
| - <!-- IFPC - inter-frame power collapse --> |
| - <value value="0x100" name="RM6_IFPC_ENABLE"/> |
| - <value value="0x101" name="RM6_IFPC_DISABLE"/> |
| </enum> |
| <reg32 offset="0" name="0"> |
| + <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> |
| + <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> |
| + |
| + <bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> |
| + <!-- used by preemption to determine if GMEM needs to be saved or not --> |
| + <bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> |
| + |
| + <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> |
| + |
| <!-- |
| - NOTE: blob driver and some versions of freedreno/turnip set |
| - b4, which is unused (at least by current sqe fw), but interferes |
| - with parsing if we extend the size of the bitfield to include |
| - b8 (only sent by kernel mode driver). Really, the way the |
| - parsing works in the firmware, only b0-b3 are considered, but |
| - if b8 is set, the low bits are interpreted differently. To |
| - model this, without getting confused by spurious b4, this is |
| - described as two overlapping bitfields: |
| - --> |
| - <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/> |
| - <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/> |
| + CP_SET_MARKER is used with these bits to create a |
| + critical section around a workaround for ray tracing. |
| + The workaround happens after BVH building, and appears |
| + to invalidate the RTU's BVH node cache. It makes sure |
| + that only one of BR/BV/LPAC is executing the |
| + workaround at a time, and no draws using RT on BV/LPAC |
| + are executing while the workaround is executed on BR (or |
| + vice versa, that no draws on BV/BR using RT are executed |
| + while the workaround executes on LPAC), by |
| + hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS. |
| + The blob usage is: |
| + |
| + CP_SET_MARKER(RT_WA_START) |
| + ... workaround here ... |
| + CP_SET_MARKER(RT_WA_END) |
| + ... |
| + CP_SET_MARKER(SHADER_USES_RT) |
| + CP_DRAW_INDX(...) or CP_EXEC_CS(...) |
| + --> |
| + <bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/> |
| + <bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/> |
| + <bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/> |
| </reg32> |
| </domain> |
| |
| @@ -1832,9 +1946,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| If concurrent binning is disabled then BR also does binning so it will also |
| write the "real" registers in BR. |
| --> |
| - <value value="8" name="DRAW_STRM_ADDRESS"/> |
| - <value value="9" name="DRAW_STRM_SIZE_ADDRESS"/> |
| - <value value="10" name="PRIM_STRM_ADDRESS"/> |
| + <value value="8" name="VSC_PIPE_DATA_DRAW_BASE"/> |
| + <value value="9" name="VSC_SIZE_BASE"/> |
| + <value value="10" name="VSC_PIPE_DATA_PRIM_BASE"/> |
| <value value="11" name="UNK_STRM_ADDRESS"/> |
| <value value="12" name="UNK_STRM_SIZE_ADDRESS"/> |
| |
| @@ -1935,11 +2049,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| a bitmask of which modes pass the test. |
| --> |
| |
| - <!-- RM6_BINNING --> |
| + <!-- RM6_BIN_VISIBILITY --> |
| <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/> |
| <!-- all others --> |
| <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/> |
| - <!-- RM6_BYPASS --> |
| + <!-- RM6_DIRECT_RENDER --> |
| <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/> |
| |
| <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/> |
| @@ -2014,10 +2128,10 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| |
| <domain name="CP_SET_AMBLE" width="32"> |
| <doc> |
| - Used by the userspace and kernel drivers to set various IB's |
| - which are executed during context save/restore for handling |
| - state that isn't restored by the context switch routine itself. |
| - </doc> |
| + Used by the userspace and kernel drivers to set various IB's |
| + which are executed during context save/restore for handling |
| + state that isn't restored by the context switch routine itself. |
| + </doc> |
| <enum name="amble_type"> |
| <value name="PREAMBLE_AMBLE_TYPE" value="0"> |
| <doc>Executed unconditionally when switching back to the context.</doc> |
| @@ -2087,12 +2201,12 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| <value name="UNK_EVENT_WRITE" value="0x4"/> |
| <doc> |
| Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and |
| - GRAS_LRZ_DEPTH_VIEW with previous values, and if one of |
| + GRAS_LRZ_VIEW_INFO with previous values, and if one of |
| the following is true: |
| - GRAS_LRZ_CNTL::GREATER has changed |
| - GRAS_LRZ_CNTL::DIR has changed, the old value is not |
| CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED |
| - - GRAS_LRZ_DEPTH_VIEW has changed |
| + - GRAS_LRZ_VIEW_INFO has changed |
| then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE |
| forced to 1. |
| Only exists in a650_sqe.fw. |
| @@ -2207,7 +2321,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| |
| <domain name="CP_MEM_TO_SCRATCH_MEM" width="32"> |
| <doc> |
| - Best guess is that it is a faster way to fetch all the VSC_STATE registers |
| + Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers |
| and keep them in a local scratch memory instead of fetching every time |
| when skipping IBs. |
| </doc> |
| @@ -2260,6 +2374,16 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) |
| </reg32> |
| </domain> |
| |
| +<domain name="CP_SCOPE_CNTL" width="32"> |
| + <enum name="cp_scope"> |
| + <value value="0" name="INTERRUPTS"/> |
| + </enum> |
| + <reg32 offset="0" name="0"> |
| + <bitfield name="DISABLE_PREEMPTION" pos="0" type="boolean"/> |
| + <bitfield low="28" high="31" name="SCOPE" type="cp_scope"/> |
| + </reg32> |
| +</domain> |
| + |
| <domain name="CP_INDIRECT_BUFFER" width="32" varset="chip" prefix="chip" variants="A5XX-"> |
| <reg64 offset="0" name="IB_BASE" type="address"/> |
| <reg32 offset="2" name="2"> |
| -- |
| 2.39.5 |
| |
