| From 6a12aaab5b7fb93f8217008140ced8505cc399df Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 12 Jul 2023 16:50:15 -0400 |
| Subject: drm/amd/display: Exit idle optimizations before attempt to access PHY |
| |
| From: Leo Chen <sancchen@amd.com> |
| |
| [ Upstream commit de612738e9771bd66aeb20044486c457c512f684 ] |
| |
| [Why & How] |
| DMUB may hang when powering down pixel clocks due to no dprefclk. |
| |
| It is fixed by exiting idle optimization before the attempt to access PHY. |
| |
| Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
| Acked-by: Alex Hung <alex.hung@amd.com> |
| Signed-off-by: Leo Chen <sancchen@amd.com> |
| Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++ |
| 1 file changed, 3 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |
| index 58e8fda04b861..ad28fdd87797f 100644 |
| --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |
| +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |
| @@ -1795,10 +1795,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) |
| hws->funcs.edp_backlight_control(edp_link_with_sink, false); |
| } |
| /*resume from S3, no vbios posting, no need to power down again*/ |
| + clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); |
| + |
| power_down_all_hw_blocks(dc); |
| disable_vga_and_power_gate_all_controllers(dc); |
| if (edp_link_with_sink && !keep_edp_vdd_on) |
| dc->hwss.edp_power_control(edp_link_with_sink, false); |
| + clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); |
| } |
| bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); |
| } |
| -- |
| 2.40.1 |
| |
