| From 85fa532b6ef920b32598df86b194571a7059a77c Mon Sep 17 00:00:00 2001 |
| From: Mike Dyer <mike.dyer@md-soft.co.uk> |
| Date: Fri, 16 Aug 2013 18:36:28 +0100 |
| Subject: ASoC: wm8960: Fix PLL register writes |
| |
| From: Mike Dyer <mike.dyer@md-soft.co.uk> |
| |
| commit 85fa532b6ef920b32598df86b194571a7059a77c upstream. |
| |
| Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part |
| should be split across each register in 8bit chunks. |
| |
| Signed-off-by: Mike Dyer <mike.dyer@md-soft.co.uk> |
| Signed-off-by: Mark Brown <broonie@linaro.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| sound/soc/codecs/wm8960.c | 6 +++--- |
| 1 file changed, 3 insertions(+), 3 deletions(-) |
| |
| --- a/sound/soc/codecs/wm8960.c |
| +++ b/sound/soc/codecs/wm8960.c |
| @@ -857,9 +857,9 @@ static int wm8960_set_dai_pll(struct snd |
| if (pll_div.k) { |
| reg |= 0x20; |
| |
| - snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f); |
| - snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff); |
| - snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff); |
| + snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); |
| + snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); |
| + snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); |
| } |
| snd_soc_write(codec, WM8960_PLL1, reg); |
| |
