| From 7d64ac6422092adbbdaa279ab32f9d4c90a84558 Mon Sep 17 00:00:00 2001 |
| From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> |
| Date: Fri, 2 Aug 2013 17:43:03 -0500 |
| Subject: x86, amd_nb: Clarify F15h, model 30h GART and L3 support |
| |
| From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> |
| |
| commit 7d64ac6422092adbbdaa279ab32f9d4c90a84558 upstream. |
| |
| F15h, models 0x30 and later don't have a GART. Note that. Also check |
| CPUID leaf 0x80000006 for L3 prescence because there are models which |
| don't sport an L3 cache. |
| |
| Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> |
| [ Boris: rewrite commit message, cleanup comments. ] |
| Signed-off-by: Borislav Petkov <bp@suse.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/x86/kernel/amd_nb.c | 13 +++++++++++-- |
| 1 file changed, 11 insertions(+), 2 deletions(-) |
| |
| --- a/arch/x86/kernel/amd_nb.c |
| +++ b/arch/x86/kernel/amd_nb.c |
| @@ -20,6 +20,7 @@ const struct pci_device_id amd_nb_misc_i |
| { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, |
| { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, |
| { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, |
| + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, |
| { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, |
| {} |
| }; |
| @@ -27,6 +28,7 @@ EXPORT_SYMBOL(amd_nb_misc_ids); |
| |
| static const struct pci_device_id amd_nb_link_ids[] = { |
| { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, |
| + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) }, |
| { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) }, |
| {} |
| }; |
| @@ -81,13 +83,20 @@ int amd_cache_northbridges(void) |
| next_northbridge(misc, amd_nb_misc_ids); |
| node_to_amd_nb(i)->link = link = |
| next_northbridge(link, amd_nb_link_ids); |
| - } |
| + } |
| |
| + /* GART present only on Fam15h upto model 0fh */ |
| if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || |
| - boot_cpu_data.x86 == 0x15) |
| + (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) |
| amd_northbridges.flags |= AMD_NB_GART; |
| |
| /* |
| + * Check for L3 cache presence. |
| + */ |
| + if (!cpuid_edx(0x80000006)) |
| + return 0; |
| + |
| + /* |
| * Some CPU families support L3 Cache Index Disable. There are some |
| * limitations because of E382 and E388 on family 0x10. |
| */ |
