| From d3694d4fa3f44f6a295f8ab064937c8a1549d174 Mon Sep 17 00:00:00 2001 |
| From: Bjorn Helgaas <bhelgaas@google.com> |
| Date: Tue, 27 Aug 2013 09:54:40 -0600 |
| Subject: PCI: Allow PCIe Capability link-related register access for switches |
| |
| From: Bjorn Helgaas <bhelgaas@google.com> |
| |
| commit d3694d4fa3f44f6a295f8ab064937c8a1549d174 upstream. |
| |
| Every PCIe device has a link, except Root Complex Integrated Endpoints |
| and Root Complex Event Collectors. Previously we didn't give access |
| to PCIe capability link-related registers for Upstream Ports, Downstream |
| Ports, and Bridges, so attempts to read PCI_EXP_LNKCTL incorrectly |
| returned zero. See PCIe spec r3.0, sec 7.8 and 1.3.2.3. |
| |
| Reference: http://lkml.kernel.org/r/979A8436335E3744ADCD3A9F2A2B68A52AD136BE@SJEXCHMB10.corp.ad.broadcom.com |
| Reported-by: Yuval Mintz <yuvalmin@broadcom.com> |
| Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
| Reviewed-By: Jiang Liu <jiang.liu@huawei.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/pci/access.c | 8 ++++++-- |
| 1 file changed, 6 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/pci/access.c |
| +++ b/drivers/pci/access.c |
| @@ -485,9 +485,13 @@ static inline bool pcie_cap_has_lnkctl(c |
| int type = pci_pcie_type(dev); |
| |
| return pcie_cap_version(dev) > 1 || |
| - type == PCI_EXP_TYPE_ROOT_PORT || |
| type == PCI_EXP_TYPE_ENDPOINT || |
| - type == PCI_EXP_TYPE_LEG_END; |
| + type == PCI_EXP_TYPE_LEG_END || |
| + type == PCI_EXP_TYPE_ROOT_PORT || |
| + type == PCI_EXP_TYPE_UPSTREAM || |
| + type == PCI_EXP_TYPE_DOWNSTREAM || |
| + type == PCI_EXP_TYPE_PCI_BRIDGE || |
| + type == PCI_EXP_TYPE_PCIE_BRIDGE; |
| } |
| |
| static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) |
