| From 8facf26623fdde6776dd908552ab490e57bf564d Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Sun, 29 Mar 2020 13:41:16 +0100 |
| Subject: clk: qcom: msm8916: Fix the address location of pll->config_reg |
| |
| From: Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
| |
| [ Upstream commit f47ab3c2f5338828a67e89d5f688d2cef9605245 ] |
| |
| During the process of debugging a processor derived from the msm8916 which |
| we found the new processor was not starting one of its PLLs. |
| |
| After tracing the addresses and writes that downstream was doing and |
| comparing to upstream it became obvious that we were writing to a different |
| register location than downstream when trying to configure the PLL. |
| |
| This error is also present in upstream msm8916. |
| |
| As an example clk-pll.c::clk_pll_recalc_rate wants to write to |
| pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is |
| defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an |
| example |
| |
| lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf |
| |
| 0x01823010 GCC_BIMC_PLL_USER_CTL |
| 0x01823014 GCC_BIMC_PLL_CONFIG_CTL |
| |
| This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll. |
| |
| This error is likely not apparent since the bootloader will already have |
| initialized these PLLs. |
| |
| This patch corrects the location of config_reg from PLL_CONFIG_CTL to |
| PLL_USER_CTL for all relevant PLLs on msm8916. |
| |
| Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") |
| |
| Cc: Georgi Djakov <georgi.djakov@linaro.org> |
| Cc: Andy Gross <agross@kernel.org> |
| Cc: Bjorn Andersson <bjorn.andersson@linaro.org> |
| Cc: Michael Turquette <mturquette@baylibre.com> |
| Cc: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
| Link: https://lkml.kernel.org/r/20200329124116.4185447-1-bryan.odonoghue@linaro.org |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/qcom/gcc-msm8916.c | 8 ++++---- |
| 1 file changed, 4 insertions(+), 4 deletions(-) |
| |
| diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c |
| index 2057809219f4e..7426d910e0797 100644 |
| --- a/drivers/clk/qcom/gcc-msm8916.c |
| +++ b/drivers/clk/qcom/gcc-msm8916.c |
| @@ -270,7 +270,7 @@ static struct clk_pll gpll0 = { |
| .l_reg = 0x21004, |
| .m_reg = 0x21008, |
| .n_reg = 0x2100c, |
| - .config_reg = 0x21014, |
| + .config_reg = 0x21010, |
| .mode_reg = 0x21000, |
| .status_reg = 0x2101c, |
| .status_bit = 17, |
| @@ -297,7 +297,7 @@ static struct clk_pll gpll1 = { |
| .l_reg = 0x20004, |
| .m_reg = 0x20008, |
| .n_reg = 0x2000c, |
| - .config_reg = 0x20014, |
| + .config_reg = 0x20010, |
| .mode_reg = 0x20000, |
| .status_reg = 0x2001c, |
| .status_bit = 17, |
| @@ -324,7 +324,7 @@ static struct clk_pll gpll2 = { |
| .l_reg = 0x4a004, |
| .m_reg = 0x4a008, |
| .n_reg = 0x4a00c, |
| - .config_reg = 0x4a014, |
| + .config_reg = 0x4a010, |
| .mode_reg = 0x4a000, |
| .status_reg = 0x4a01c, |
| .status_bit = 17, |
| @@ -351,7 +351,7 @@ static struct clk_pll bimc_pll = { |
| .l_reg = 0x23004, |
| .m_reg = 0x23008, |
| .n_reg = 0x2300c, |
| - .config_reg = 0x23014, |
| + .config_reg = 0x23010, |
| .mode_reg = 0x23000, |
| .status_reg = 0x2301c, |
| .status_bit = 17, |
| -- |
| 2.25.1 |
| |