| From foo@baz Wed Aug 9 11:19:16 PDT 2017 |
| From: Grygorii Strashko <grygorii.strashko@ti.com> |
| Date: Thu, 5 Jan 2017 14:48:07 -0600 |
| Subject: net: phy: dp83867: fix irq generation |
| |
| From: Grygorii Strashko <grygorii.strashko@ti.com> |
| |
| |
| [ Upstream commit 5ca7d1ca77dc23934504b95a96d2660d345f83c2 ] |
| |
| For proper IRQ generation by DP83867 phy the INT/PWDN pin has to be |
| programmed as an interrupt output instead of a Powerdown input in |
| Configuration Register 3 (CFG3), Address 0x001E, bit 7 INT_OE = 1. The |
| current driver doesn't do this and as result IRQs will not be generated by |
| DP83867 phy even if they are properly configured in DT. |
| |
| Hence, fix IRQ generation by properly configuring CFG3.INT_OE bit and |
| ensure that Link Status Change (LINK_STATUS_CHNG_INT) and Auto-Negotiation |
| Complete (AUTONEG_COMP_INT) interrupt are enabled. After this the DP83867 |
| driver will work properly in interrupt enabled mode. |
| |
| Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> |
| Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Sasha Levin <alexander.levin@verizon.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/net/phy/dp83867.c | 10 ++++++++++ |
| 1 file changed, 10 insertions(+) |
| |
| --- a/drivers/net/phy/dp83867.c |
| +++ b/drivers/net/phy/dp83867.c |
| @@ -29,6 +29,7 @@ |
| #define MII_DP83867_MICR 0x12 |
| #define MII_DP83867_ISR 0x13 |
| #define DP83867_CTRL 0x1f |
| +#define DP83867_CFG3 0x1e |
| |
| /* Extended Registers */ |
| #define DP83867_RGMIICTL 0x0032 |
| @@ -89,6 +90,8 @@ static int dp83867_config_intr(struct ph |
| micr_status |= |
| (MII_DP83867_MICR_AN_ERR_INT_EN | |
| MII_DP83867_MICR_SPEED_CHNG_INT_EN | |
| + MII_DP83867_MICR_AUTONEG_COMP_INT_EN | |
| + MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | |
| MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | |
| MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); |
| |
| @@ -184,6 +187,13 @@ static int dp83867_config_init(struct ph |
| DP83867_DEVADDR, phydev->addr, delay); |
| } |
| |
| + /* Enable Interrupt output INT_OE in CFG3 register */ |
| + if (phy_interrupt_is_valid(phydev)) { |
| + val = phy_read(phydev, DP83867_CFG3); |
| + val |= BIT(7); |
| + phy_write(phydev, DP83867_CFG3, val); |
| + } |
| + |
| return 0; |
| } |
| |