| From df655b75c43fba0f2621680ab261083297fd6d16 Mon Sep 17 00:00:00 2001 |
| From: Will Deacon <will.deacon@arm.com> |
| Date: Thu, 13 Dec 2018 16:06:14 +0000 |
| Subject: arm64: KVM: Avoid setting the upper 32 bits of VTCR_EL2 to 1 |
| |
| From: Will Deacon <will.deacon@arm.com> |
| |
| commit df655b75c43fba0f2621680ab261083297fd6d16 upstream. |
| |
| Although bit 31 of VTCR_EL2 is RES1, we inadvertently end up setting all |
| of the upper 32 bits to 1 as well because we define VTCR_EL2_RES1 as |
| signed, which is sign-extended when assigning to kvm->arch.vtcr. |
| |
| Lucky for us, the architecture currently treats these upper bits as RES0 |
| so, whilst we've been naughty, we haven't set fire to anything yet. |
| |
| Cc: <stable@vger.kernel.org> |
| Cc: Marc Zyngier <marc.zyngier@arm.com> |
| Cc: Christoffer Dall <christoffer.dall@arm.com> |
| Signed-off-by: Will Deacon <will.deacon@arm.com> |
| Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm64/include/asm/kvm_arm.h | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/arch/arm64/include/asm/kvm_arm.h |
| +++ b/arch/arm64/include/asm/kvm_arm.h |
| @@ -99,7 +99,7 @@ |
| TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) |
| |
| /* VTCR_EL2 Registers bits */ |
| -#define VTCR_EL2_RES1 (1 << 31) |
| +#define VTCR_EL2_RES1 (1U << 31) |
| #define VTCR_EL2_HD (1 << 22) |
| #define VTCR_EL2_HA (1 << 21) |
| #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK |
