| From foo@baz Mon Apr 9 17:09:24 CEST 2018 |
| From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Date: Sun, 4 Jun 2017 20:33:39 +0200 |
| Subject: clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 |
| |
| From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| |
| |
| [ Upstream commit 855f06a1009faabb0c6a3e9b49d115496d325856 ] |
| |
| The clock controller on Meson8, Meson8b and Meson8m2 is very similar |
| based on the code from the Amlogic GPL kernel sources. Add separate |
| compatibles for each SoC to make sure that we can easily implement |
| all the small differences for each SoC later on. |
| |
| In general the Meson8 and Meson8m2 seem to be almost identical as they |
| even share the same mach-meson8 directory in Amlogic's GPL kernel |
| sources. |
| The main clocks on Meson8, Meson8b and Meson8m2 are very similar, |
| because they are all using the same PLL values, 90% of the clock gates |
| are the same (the actual diffstat of the mach-meson8/clock.c and |
| mach-meson8b/clock.c files is around 30 to 40 lines, when excluding |
| all commented out code). |
| The difference between the Meson8 and Meson8b clock gates seem to be: |
| - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, |
| CSI_DIG_CLKIN gates which don't seem to be available on Meson8b |
| - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead |
| of "PERIPHS_TOP" (on Meson8b) |
| - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or |
| on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL |
| kernel sources) |
| None of these gates is added for now, since it's unclear whether these |
| definitions are actually correct (the VCLK2_ENCT gate for example is |
| defined, but only used in some commented block). |
| |
| The main difference between all three SoCs seem to be the video (VPU) |
| clocks. Apart from different supported clock rates (according to vpu.c |
| in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the |
| most notable difference is that Meson8m2 has a GP_PLL clock and a mux |
| (probably the same as on the Meson GX SoCs) to support glitch-free |
| (clock rate) switching. |
| None of these VPU clocks are not supported by our mainline meson8b |
| clock driver yet though. |
| |
| Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Acked-by: Rob Herring <robh@kernel.org> |
| Acked-by: Kevin Hilman <khilman@baylibre.com> |
| Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 11 ++++++---- |
| drivers/clk/meson/Kconfig | 6 ++--- |
| drivers/clk/meson/meson8b.c | 5 +++- |
| 3 files changed, 14 insertions(+), 8 deletions(-) |
| |
| --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt |
| +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt |
| @@ -1,11 +1,14 @@ |
| -* Amlogic Meson8b Clock and Reset Unit |
| +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit |
| |
| -The Amlogic Meson8b clock controller generates and supplies clock to various |
| -controllers within the SoC. |
| +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and |
| +supplies clock to various controllers within the SoC. |
| |
| Required Properties: |
| |
| -- compatible: should be "amlogic,meson8b-clkc" |
| +- compatible: must be one of: |
| + - "amlogic,meson8-clkc" for Meson8 (S802) SoCs |
| + - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs |
| + - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs |
| - reg: it must be composed by two tuples: |
| 0) physical base address of the xtal register and length of memory |
| mapped region. |
| --- a/drivers/clk/meson/Kconfig |
| +++ b/drivers/clk/meson/Kconfig |
| @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B |
| bool |
| depends on COMMON_CLK_AMLOGIC |
| help |
| - Support for the clock controller on AmLogic S805 devices, aka |
| - meson8b. Say Y if you want peripherals and CPU frequency scaling to |
| - work. |
| + Support for the clock controller on AmLogic S802 (Meson8), |
| + S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you |
| + want peripherals and CPU frequency scaling to work. |
| |
| config COMMON_CLK_GXBB |
| bool |
| --- a/drivers/clk/meson/meson8b.c |
| +++ b/drivers/clk/meson/meson8b.c |
| @@ -1,5 +1,6 @@ |
| /* |
| - * AmLogic S805 / Meson8b Clock Controller Driver |
| + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller |
| + * Driver |
| * |
| * Copyright (c) 2015 Endless Mobile, Inc. |
| * Author: Carlo Caione <carlo@endlessm.com> |
| @@ -661,7 +662,9 @@ iounmap: |
| } |
| |
| static const struct of_device_id meson8b_clkc_match_table[] = { |
| + { .compatible = "amlogic,meson8-clkc" }, |
| { .compatible = "amlogic,meson8b-clkc" }, |
| + { .compatible = "amlogic,meson8m2-clkc" }, |
| { } |
| }; |
| |