| From foo@baz Mon Apr 9 17:09:24 CEST 2018 |
| From: Ganesh Goudar <ganeshgr@chelsio.com> |
| Date: Wed, 31 May 2017 19:10:21 +0530 |
| Subject: cxgb4: fix incorrect cim_la output for T6 |
| |
| From: Ganesh Goudar <ganeshgr@chelsio.com> |
| |
| |
| [ Upstream commit a97051f4553551d13e586ab3cb6ae13093a44a81 ] |
| |
| take care of UpDbgLaRdPtr[0-3] restriction for T6. |
| |
| Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 11 ++++++++++- |
| 1 file changed, 10 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c |
| +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c |
| @@ -8088,7 +8088,16 @@ int t4_cim_read_la(struct adapter *adap, |
| ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); |
| if (ret) |
| break; |
| - idx = (idx + 1) & UPDBGLARDPTR_M; |
| + |
| + /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to |
| + * identify the 32-bit portion of the full 312-bit data |
| + */ |
| + if (is_t6(adap->params.chip) && (idx & 0xf) >= 9) |
| + idx = (idx & 0xff0) + 0x10; |
| + else |
| + idx++; |
| + /* address can't exceed 0xfff */ |
| + idx &= UPDBGLARDPTR_M; |
| } |
| restart: |
| if (cfg & UPDBGLAEN_F) { |
