| From foo@baz Mon Apr 9 17:09:24 CEST 2018 |
| From: "Maciej S. Szmigiero" <mail@maciej.szmigiero.name> |
| Date: Mon, 17 Apr 2017 22:37:05 +0200 |
| Subject: watchdog: f71808e_wdt: Add F71868 support |
| |
| From: "Maciej S. Szmigiero" <mail@maciej.szmigiero.name> |
| |
| |
| [ Upstream commit 166fbcf88fdafa02f784ec25ac64745c716b2de0 ] |
| |
| This adds support for watchdog part of Fintek F71868 Super I/O chip to |
| f71808e_wdt driver. |
| |
| The F71868 chip is, in general, very similar to a F71869, however it has |
| slightly different set of available reset pulse widths. |
| |
| Tested on MSI A55M-P33 motherboard. |
| |
| Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> |
| Reviewed-by: Guenter Roeck <linux@roeck-us.net> |
| Signed-off-by: Guenter Roeck <linux@roeck-us.net> |
| Signed-off-by: Wim Van Sebroeck <wim@iguana.be> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/watchdog/Kconfig | 7 ++++--- |
| drivers/watchdog/f71808e_wdt.c | 27 ++++++++++++++++++++------- |
| 2 files changed, 24 insertions(+), 10 deletions(-) |
| |
| --- a/drivers/watchdog/Kconfig |
| +++ b/drivers/watchdog/Kconfig |
| @@ -799,11 +799,12 @@ config EBC_C384_WDT |
| the timeout module parameter. |
| |
| config F71808E_WDT |
| - tristate "Fintek F71808E, F71862FG, F71869, F71882FG and F71889FG Watchdog" |
| + tristate "Fintek F718xx, F818xx Super I/O Watchdog" |
| depends on X86 |
| help |
| - This is the driver for the hardware watchdog on the Fintek |
| - F71808E, F71862FG, F71869, F71882FG and F71889FG Super I/O controllers. |
| + This is the driver for the hardware watchdog on the Fintek F71808E, |
| + F71862FG, F71868, F71869, F71882FG, F71889FG, F81865 and F81866 |
| + Super I/O controllers. |
| |
| You can compile this driver directly into the kernel, or use |
| it as a module. The module will be called f71808e_wdt. |
| --- a/drivers/watchdog/f71808e_wdt.c |
| +++ b/drivers/watchdog/f71808e_wdt.c |
| @@ -57,6 +57,7 @@ |
| #define SIO_F71808_ID 0x0901 /* Chipset ID */ |
| #define SIO_F71858_ID 0x0507 /* Chipset ID */ |
| #define SIO_F71862_ID 0x0601 /* Chipset ID */ |
| +#define SIO_F71868_ID 0x1106 /* Chipset ID */ |
| #define SIO_F71869_ID 0x0814 /* Chipset ID */ |
| #define SIO_F71869A_ID 0x1007 /* Chipset ID */ |
| #define SIO_F71882_ID 0x0541 /* Chipset ID */ |
| @@ -101,7 +102,7 @@ MODULE_PARM_DESC(timeout, |
| static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH; |
| module_param(pulse_width, uint, 0); |
| MODULE_PARM_DESC(pulse_width, |
| - "Watchdog signal pulse width. 0(=level), 1 ms, 25 ms, 125 ms or 5000 ms" |
| + "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms" |
| " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")"); |
| |
| static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN; |
| @@ -119,13 +120,14 @@ module_param(start_withtimeout, uint, 0) |
| MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with" |
| " given initial timeout. Zero (default) disables this feature."); |
| |
| -enum chips { f71808fg, f71858fg, f71862fg, f71869, f71882fg, f71889fg, f81865, |
| - f81866}; |
| +enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg, |
| + f81865, f81866}; |
| |
| static const char *f71808e_names[] = { |
| "f71808fg", |
| "f71858fg", |
| "f71862fg", |
| + "f71868", |
| "f71869", |
| "f71882fg", |
| "f71889fg", |
| @@ -252,16 +254,23 @@ static int watchdog_set_timeout(int time |
| static int watchdog_set_pulse_width(unsigned int pw) |
| { |
| int err = 0; |
| + unsigned int t1 = 25, t2 = 125, t3 = 5000; |
| + |
| + if (watchdog.type == f71868) { |
| + t1 = 30; |
| + t2 = 150; |
| + t3 = 6000; |
| + } |
| |
| mutex_lock(&watchdog.lock); |
| |
| - if (pw <= 1) { |
| + if (pw <= 1) { |
| watchdog.pulse_val = 0; |
| - } else if (pw <= 25) { |
| + } else if (pw <= t1) { |
| watchdog.pulse_val = 1; |
| - } else if (pw <= 125) { |
| + } else if (pw <= t2) { |
| watchdog.pulse_val = 2; |
| - } else if (pw <= 5000) { |
| + } else if (pw <= t3) { |
| watchdog.pulse_val = 3; |
| } else { |
| pr_err("pulse width out of range\n"); |
| @@ -354,6 +363,7 @@ static int watchdog_start(void) |
| goto exit_superio; |
| break; |
| |
| + case f71868: |
| case f71869: |
| /* GPIO14 --> WDTRST# */ |
| superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4); |
| @@ -792,6 +802,9 @@ static int __init f71808e_find(int sioad |
| watchdog.type = f71862fg; |
| err = f71862fg_pin_configure(0); /* validate module parameter */ |
| break; |
| + case SIO_F71868_ID: |
| + watchdog.type = f71868; |
| + break; |
| case SIO_F71869_ID: |
| case SIO_F71869A_ID: |
| watchdog.type = f71869; |