| From ada637e70f96862ff5ba20a169506b58cf567db9 Mon Sep 17 00:00:00 2001 |
| From: Harry Wentland <harry.wentland@amd.com> |
| Date: Tue, 14 May 2019 09:05:37 -0400 |
| Subject: drm/amd/display: Add ASICREV_IS_PICASSO |
| |
| From: Harry Wentland <harry.wentland@amd.com> |
| |
| commit ada637e70f96862ff5ba20a169506b58cf567db9 upstream. |
| |
| [WHY] |
| We only want to load DMCU FW on Picasso and Raven 2, not on Raven 1. |
| |
| Signed-off-by: Harry Wentland <harry.wentland@amd.com> |
| Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 ++++--- |
| 1 file changed, 4 insertions(+), 3 deletions(-) |
| |
| --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h |
| +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h |
| @@ -138,13 +138,14 @@ |
| #endif |
| #define RAVEN_UNKNOWN 0xFF |
| |
| -#if defined(CONFIG_DRM_AMD_DC_DCN1_01) |
| -#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0)) |
| -#endif /* DCN1_01 */ |
| #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) |
| #define RAVEN1_F0 0xF0 |
| #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN)) |
| |
| +#if defined(CONFIG_DRM_AMD_DC_DCN1_01) |
| +#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0)) |
| +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0)) |
| +#endif /* DCN1_01 */ |
| |
| #define FAMILY_RV 142 /* DCN 1*/ |
| |
