| From dfd1427c3769ba51297777dbb296f1802d72dbf6 Mon Sep 17 00:00:00 2001 |
| From: Dinh Nguyen <dinguyen@kernel.org> |
| Date: Thu, 10 Jun 2021 21:52:01 -0500 |
| Subject: clk: agilex/stratix10/n5x: fix how the bypass_reg is handled |
| |
| From: Dinh Nguyen <dinguyen@kernel.org> |
| |
| commit dfd1427c3769ba51297777dbb296f1802d72dbf6 upstream. |
| |
| If the bypass_reg is set, then we can return the bypass parent, however, |
| if there is not a bypass_reg, we need to figure what the correct parent |
| mux is. |
| |
| The previous code never handled the parent mux if there was a |
| bypass_reg. |
| |
| Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
| Link: https://lore.kernel.org/r/20210611025201.118799-4-dinguyen@kernel.org |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/clk/socfpga/clk-periph-s10.c | 11 ++++++++--- |
| 1 file changed, 8 insertions(+), 3 deletions(-) |
| |
| --- a/drivers/clk/socfpga/clk-periph-s10.c |
| +++ b/drivers/clk/socfpga/clk-periph-s10.c |
| @@ -49,16 +49,21 @@ static u8 clk_periclk_get_parent(struct |
| { |
| struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); |
| u32 clk_src, mask; |
| - u8 parent; |
| + u8 parent = 0; |
| |
| + /* handle the bypass first */ |
| if (socfpgaclk->bypass_reg) { |
| mask = (0x1 << socfpgaclk->bypass_shift); |
| parent = ((readl(socfpgaclk->bypass_reg) & mask) >> |
| socfpgaclk->bypass_shift); |
| - } else { |
| + if (parent) |
| + return parent; |
| + } |
| + |
| + if (socfpgaclk->hw.reg) { |
| clk_src = readl(socfpgaclk->hw.reg); |
| parent = (clk_src >> CLK_MGR_FREE_SHIFT) & |
| - CLK_MGR_FREE_MASK; |
| + CLK_MGR_FREE_MASK; |
| } |
| return parent; |
| } |