| From efbe21df3e889c0f4bf682c2b7e2465d60b0127c Mon Sep 17 00:00:00 2001 |
| From: Dinh Nguyen <dinguyen@kernel.org> |
| Date: Thu, 10 Jun 2021 21:51:58 -0500 |
| Subject: clk: agilex/stratix10: remove noc_clk |
| |
| From: Dinh Nguyen <dinguyen@kernel.org> |
| |
| commit efbe21df3e889c0f4bf682c2b7e2465d60b0127c upstream. |
| |
| Early documentation had a noc_clk, but in reality, it's just the |
| noc_free_clk. Remove the noc_clk clock and just use the noc_free_clk. |
| |
| Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
| Link: https://lore.kernel.org/r/20210611025201.118799-1-dinguyen@kernel.org |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/clk/socfpga/clk-agilex.c | 32 +++++++++++++++----------------- |
| drivers/clk/socfpga/clk-s10.c | 32 +++++++++++++++----------------- |
| 2 files changed, 30 insertions(+), 34 deletions(-) |
| |
| --- a/drivers/clk/socfpga/clk-agilex.c |
| +++ b/drivers/clk/socfpga/clk-agilex.c |
| @@ -211,11 +211,9 @@ static const struct stratix10_perip_cnt_ |
| { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux), |
| 0, 0x3C, 0, 0, 0}, |
| { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux), |
| - 0, 0x40, 0, 0, 1}, |
| - { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0, |
| - 0, 4, 0, 0}, |
| - { AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), |
| - 0, 0, 0, 0x30, 1}, |
| + 0, 0x40, 0, 0, 0}, |
| + { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, |
| + 0, 4, 0x30, 1}, |
| { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), |
| 0, 0xD4, 0, 0x88, 0}, |
| { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), |
| @@ -241,24 +239,24 @@ static const struct stratix10_gate_clock |
| 0, 0, 0, 0, 0, 0, 4}, |
| { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24, |
| 0, 0, 0, 0, 0, 0, 2}, |
| - { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24, |
| - 1, 0x44, 0, 2, 0, 0, 0}, |
| - { AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24, |
| - 2, 0x44, 8, 2, 0, 0, 0}, |
| + { AGILEX_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, |
| + 1, 0x44, 0, 2, 0x30, 1, 0}, |
| + { AGILEX_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, |
| + 2, 0x44, 8, 2, 0x30, 1, 0}, |
| /* |
| * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them |
| * being the SP timers, thus cannot get gated. |
| */ |
| - { AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24, |
| - 3, 0x44, 16, 2, 0, 0, 0}, |
| - { AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24, |
| - 4, 0x44, 24, 2, 0, 0, 0}, |
| - { AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24, |
| - 4, 0x44, 26, 2, 0, 0, 0}, |
| + { AGILEX_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x24, |
| + 3, 0x44, 16, 2, 0x30, 1, 0}, |
| + { AGILEX_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, |
| + 4, 0x44, 24, 2, 0x30, 1, 0}, |
| + { AGILEX_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, |
| + 4, 0x44, 26, 2, 0x30, 1, 0}, |
| { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, |
| 4, 0x44, 28, 1, 0, 0, 0}, |
| - { AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24, |
| - 5, 0, 0, 0, 0, 0, 0}, |
| + { AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24, |
| + 5, 0, 0, 0, 0x30, 1, 0}, |
| { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24, |
| 6, 0, 0, 0, 0, 0, 0}, |
| { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C, |
| --- a/drivers/clk/socfpga/clk-s10.c |
| +++ b/drivers/clk/socfpga/clk-s10.c |
| @@ -167,7 +167,7 @@ static const struct stratix10_perip_cnt_ |
| { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux), |
| 0, 0x48, 0, 0, 0}, |
| { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux), |
| - 0, 0x4C, 0, 0, 0}, |
| + 0, 0x4C, 0, 0x3C, 1}, |
| { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0, |
| 0x50, 0, 0, 0}, |
| { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0, |
| @@ -200,10 +200,8 @@ static const struct stratix10_perip_cnt_ |
| 0, 0xD4, 0, 0, 0}, |
| { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0, |
| 0xD8, 0, 0, 0}, |
| - { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0, |
| - 0, 4, 0, 0}, |
| - { STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), |
| - 0, 0, 0, 0x3C, 1}, |
| + { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, |
| + 0, 4, 0x3C, 1}, |
| { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), |
| 0, 0, 2, 0xB0, 0}, |
| { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), |
| @@ -227,20 +225,20 @@ static const struct stratix10_gate_clock |
| 0, 0, 0, 0, 0, 0, 4}, |
| { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30, |
| 0, 0, 0, 0, 0, 0, 2}, |
| - { STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30, |
| - 1, 0x70, 0, 2, 0, 0, 0}, |
| - { STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30, |
| - 2, 0x70, 8, 2, 0, 0, 0}, |
| - { STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30, |
| - 3, 0x70, 16, 2, 0, 0, 0}, |
| - { STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30, |
| - 4, 0x70, 24, 2, 0, 0, 0}, |
| - { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30, |
| - 4, 0x70, 26, 2, 0, 0, 0}, |
| + { STRATIX10_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, |
| + 1, 0x70, 0, 2, 0x3C, 1, 0}, |
| + { STRATIX10_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, |
| + 2, 0x70, 8, 2, 0x3C, 1, 0}, |
| + { STRATIX10_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x30, |
| + 3, 0x70, 16, 2, 0x3C, 1, 0}, |
| + { STRATIX10_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, |
| + 4, 0x70, 24, 2, 0x3C, 1, 0}, |
| + { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, |
| + 4, 0x70, 26, 2, 0x3C, 1, 0}, |
| { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30, |
| 4, 0x70, 28, 1, 0, 0, 0}, |
| - { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30, |
| - 5, 0, 0, 0, 0, 0, 0}, |
| + { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30, |
| + 5, 0, 0, 0, 0x3C, 1, 0}, |
| { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30, |
| 6, 0, 0, 0, 0, 0, 0}, |
| { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, |