| From 865ee7818ecd7bd26cec28fc948abbcf9c4235d8 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 29 Apr 2021 11:03:25 +0200 |
| Subject: clk: meson: g12a: fix gp0 and hifi ranges |
| |
| From: Jerome Brunet <jbrunet@baylibre.com> |
| |
| [ Upstream commit bc794f8c56abddf709f1f84fcb2a3c9e7d9cc9b4 ] |
| |
| While some SoC samples are able to lock with a PLL factor of 55, others |
| samples can't. ATM, a minimum of 60 appears to work on all the samples |
| I have tried. |
| |
| Even with 60, it sometimes takes a long time for the PLL to eventually |
| lock. The documentation says that the minimum rate of these PLLs DCO |
| should be 3GHz, a factor of 125. Let's use that to be on the safe side. |
| |
| With factor range changed, the PLL seems to lock quickly (enough) so far. |
| It is still unclear if the range was the only reason for the delay. |
| |
| Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") |
| Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
| Acked-by: Neil Armstrong <narmstrong@baylibre.com> |
| Link: https://lore.kernel.org/r/20210429090325.60970-1-jbrunet@baylibre.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/meson/g12a.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c |
| index b814d44917a5..2876bb83d9d0 100644 |
| --- a/drivers/clk/meson/g12a.c |
| +++ b/drivers/clk/meson/g12a.c |
| @@ -1602,7 +1602,7 @@ static struct clk_regmap g12b_cpub_clk_trace = { |
| }; |
| |
| static const struct pll_mult_range g12a_gp0_pll_mult_range = { |
| - .min = 55, |
| + .min = 125, |
| .max = 255, |
| }; |
| |
| -- |
| 2.30.2 |
| |