| From 2ac0b029a04b673ce83b5089368f467c5dca720c Mon Sep 17 00:00:00 2001 |
| From: Marc Kleine-Budde <mkl@pengutronix.de> |
| Date: Thu, 10 Jun 2021 15:46:16 +0200 |
| Subject: iio: ltr501: mark register holding upper 8 bits of ALS_DATA{0,1} and PS_DATA as volatile, too |
| |
| From: Marc Kleine-Budde <mkl@pengutronix.de> |
| |
| commit 2ac0b029a04b673ce83b5089368f467c5dca720c upstream. |
| |
| The regmap is configured for 8 bit registers, uses a RB-Tree cache and |
| marks several registers as volatile (i.e. do not cache). |
| |
| The ALS and PS data registers in the chip are 16 bit wide and spans |
| two regmap registers. In the current driver only the base register is |
| marked as volatile, resulting in the upper register only read once. |
| |
| Further the data sheet notes: |
| |
| | When the I2C read operation starts, all four ALS data registers are |
| | locked until the I2C read operation of register 0x8B is completed. |
| |
| Which results in the registers never update after the 2nd read. |
| |
| This patch fixes the problem by marking the upper 8 bits of the ALS |
| and PS registers as volatile, too. |
| |
| Fixes: 2f2c96338afc ("iio: ltr501: Add regmap support.") |
| Reported-by: Oliver Lang <Oliver.Lang@gossenmetrawatt.com> |
| Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> |
| Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> |
| Tested-by: Nikita Travkin <nikita@trvn.ru> # ltr559 |
| Link: https://lore.kernel.org/r/20210610134619.2101372-2-mkl@pengutronix.de |
| Cc: <Stable@vger.kernel.org> |
| Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/iio/light/ltr501.c | 6 ++++++ |
| 1 file changed, 6 insertions(+) |
| |
| --- a/drivers/iio/light/ltr501.c |
| +++ b/drivers/iio/light/ltr501.c |
| @@ -32,9 +32,12 @@ |
| #define LTR501_PART_ID 0x86 |
| #define LTR501_MANUFAC_ID 0x87 |
| #define LTR501_ALS_DATA1 0x88 /* 16-bit, little endian */ |
| +#define LTR501_ALS_DATA1_UPPER 0x89 /* upper 8 bits of LTR501_ALS_DATA1 */ |
| #define LTR501_ALS_DATA0 0x8a /* 16-bit, little endian */ |
| +#define LTR501_ALS_DATA0_UPPER 0x8b /* upper 8 bits of LTR501_ALS_DATA0 */ |
| #define LTR501_ALS_PS_STATUS 0x8c |
| #define LTR501_PS_DATA 0x8d /* 16-bit, little endian */ |
| +#define LTR501_PS_DATA_UPPER 0x8e /* upper 8 bits of LTR501_PS_DATA */ |
| #define LTR501_INTR 0x8f /* output mode, polarity, mode */ |
| #define LTR501_PS_THRESH_UP 0x90 /* 11 bit, ps upper threshold */ |
| #define LTR501_PS_THRESH_LOW 0x92 /* 11 bit, ps lower threshold */ |
| @@ -1354,9 +1357,12 @@ static bool ltr501_is_volatile_reg(struc |
| { |
| switch (reg) { |
| case LTR501_ALS_DATA1: |
| + case LTR501_ALS_DATA1_UPPER: |
| case LTR501_ALS_DATA0: |
| + case LTR501_ALS_DATA0_UPPER: |
| case LTR501_ALS_PS_STATUS: |
| case LTR501_PS_DATA: |
| + case LTR501_PS_DATA_UPPER: |
| return true; |
| default: |
| return false; |