| From 3b4cba513f1a99bb0cd0192a4484c19fea074748 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 18 Jun 2021 11:51:39 +0100 |
| Subject: KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is |
| set |
| |
| From: Alexandru Elisei <alexandru.elisei@arm.com> |
| |
| [ Upstream commit 2a71fabf6a1bc9162a84e18d6ab991230ca4d588 ] |
| |
| According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to |
| 1 has the following effect: |
| |
| "Reset all event counters accessible in the current Exception level, not |
| including PMCCNTR_EL0, to zero." |
| |
| Similar behaviour is described for AArch32 on page G8-7022. Make it so. |
| |
| Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters") |
| Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> |
| Signed-off-by: Marc Zyngier <maz@kernel.org> |
| Link: https://lore.kernel.org/r/20210618105139.83795-1-alexandru.elisei@arm.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm64/kvm/pmu-emul.c | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c |
| index 2dd164bb1c5a..4b30260e1abf 100644 |
| --- a/arch/arm64/kvm/pmu-emul.c |
| +++ b/arch/arm64/kvm/pmu-emul.c |
| @@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) |
| kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); |
| |
| if (val & ARMV8_PMU_PMCR_P) { |
| + mask &= ~BIT(ARMV8_PMU_CYCLE_IDX); |
| for_each_set_bit(i, &mask, 32) |
| kvm_pmu_set_counter_value(vcpu, i, 0); |
| } |
| -- |
| 2.30.2 |
| |
