| From 9cddf03b2af07443bebdc73cba21acb360c079e8 Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| Date: Fri, 11 Mar 2022 23:28:45 +0200 |
| Subject: drm/i915: Reject unsupported TMDS rates on ICL+ |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| |
| commit 9cddf03b2af07443bebdc73cba21acb360c079e8 upstream. |
| |
| ICL+ PLLs can't genenerate certain frequencies. Running the PLL |
| algorithms through for all frequencies 25-594MHz we see a gap just |
| above 500 MHz. Specifically 500-522.8MHZ for TC PLLs, and 500-533.2 |
| MHz for combo PHY PLLs. Reject those frequencies hdmi_port_clock_valid() |
| so that we properly filter out unsupported modes and/or color depths |
| for HDMI. |
| |
| Cc: stable@vger.kernel.org |
| Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5247 |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Link: https://patchwork.freedesktop.org/patch/msgid/20220311212845.32358-1-ville.syrjala@linux.intel.com |
| Reviewed-by: Mika Kahola <mika.kahola@intel.com> |
| (cherry picked from commit e5086cb3f3d3f94091be29eec38cf13f8a75a778) |
| Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +++++++++ |
| 1 file changed, 9 insertions(+) |
| |
| --- a/drivers/gpu/drm/i915/display/intel_hdmi.c |
| +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c |
| @@ -1831,6 +1831,7 @@ hdmi_port_clock_valid(struct intel_hdmi |
| bool has_hdmi_sink) |
| { |
| struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); |
| + enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); |
| |
| if (clock < 25000) |
| return MODE_CLOCK_LOW; |
| @@ -1851,6 +1852,14 @@ hdmi_port_clock_valid(struct intel_hdmi |
| if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
| return MODE_CLOCK_RANGE; |
| |
| + /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ |
| + if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200) |
| + return MODE_CLOCK_RANGE; |
| + |
| + /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ |
| + if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800) |
| + return MODE_CLOCK_RANGE; |
| + |
| /* |
| * SNPS PHYs' MPLLB table-based programming can only handle a fixed |
| * set of link rates. |
