| From e81e20541dee3dacf04cde9d430115dbafbdf73d Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 26 Jun 2025 15:44:02 +0200 |
| Subject: net: fec: allow disable coalescing |
| |
| From: Jonas Rebmann <jre@pengutronix.de> |
| |
| [ Upstream commit b7ad21258f9e9a7f58b19595d5ceed2cde3bed68 ] |
| |
| In the current implementation, IP coalescing is always enabled and |
| cannot be disabled. |
| |
| As setting maximum frames to 0 or 1, or setting delay to zero implies |
| immediate delivery of single packets/IRQs, disable coalescing in |
| hardware in these cases. |
| |
| This also guarantees that coalescing is never enabled with ICFT or ICTT |
| set to zero, a configuration that could lead to unpredictable behaviour |
| according to i.MX8MP reference manual. |
| |
| Signed-off-by: Jonas Rebmann <jre@pengutronix.de> |
| Reviewed-by: Wei Fang <wei.fang@nxp.com> |
| Link: https://patch.msgid.link/20250626-fec_deactivate_coalescing-v2-1-0b217f2e80da@pengutronix.de |
| Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/net/ethernet/freescale/fec_main.c | 34 +++++++++++------------ |
| 1 file changed, 16 insertions(+), 18 deletions(-) |
| |
| diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c |
| index 4a513dba8f53..d10db5d6d226 100644 |
| --- a/drivers/net/ethernet/freescale/fec_main.c |
| +++ b/drivers/net/ethernet/freescale/fec_main.c |
| @@ -2831,27 +2831,25 @@ static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) |
| static void fec_enet_itr_coal_set(struct net_device *ndev) |
| { |
| struct fec_enet_private *fep = netdev_priv(ndev); |
| - int rx_itr, tx_itr; |
| + u32 rx_itr = 0, tx_itr = 0; |
| + int rx_ictt, tx_ictt; |
| |
| - /* Must be greater than zero to avoid unpredictable behavior */ |
| - if (!fep->rx_time_itr || !fep->rx_pkts_itr || |
| - !fep->tx_time_itr || !fep->tx_pkts_itr) |
| - return; |
| - |
| - /* Select enet system clock as Interrupt Coalescing |
| - * timer Clock Source |
| - */ |
| - rx_itr = FEC_ITR_CLK_SEL; |
| - tx_itr = FEC_ITR_CLK_SEL; |
| + rx_ictt = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); |
| + tx_ictt = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); |
| |
| - /* set ICFT and ICTT */ |
| - rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); |
| - rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); |
| - tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); |
| - tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); |
| + if (rx_ictt > 0 && fep->rx_pkts_itr > 1) { |
| + /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ |
| + rx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; |
| + rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); |
| + rx_itr |= FEC_ITR_ICTT(rx_ictt); |
| + } |
| |
| - rx_itr |= FEC_ITR_EN; |
| - tx_itr |= FEC_ITR_EN; |
| + if (tx_ictt > 0 && fep->tx_pkts_itr > 1) { |
| + /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ |
| + tx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; |
| + tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); |
| + tx_itr |= FEC_ITR_ICTT(tx_ictt); |
| + } |
| |
| writel(tx_itr, fep->hwp + FEC_TXIC0); |
| writel(rx_itr, fep->hwp + FEC_RXIC0); |
| -- |
| 2.39.5 |
| |