| From 93a7b12acca1df5256a1acd3b0460b80c429d39b Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 10 Dec 2020 22:25:22 +0100 |
| Subject: ARM: dts: exynos: correct PMIC interrupt trigger level on Odroid X/U3 |
| family |
| |
| From: Krzysztof Kozlowski <krzk@kernel.org> |
| |
| [ Upstream commit 6503c568e97a52f8b7a3109718db438e52e59485 ] |
| |
| The Maxim PMIC datasheets describe the interrupt line as active low |
| with a requirement of acknowledge from the CPU. Without specifying the |
| interrupt type in Devicetree, kernel might apply some fixed |
| configuration, not necessarily working for this hardware. |
| |
| Additionally, the interrupt line is shared so using level sensitive |
| interrupt is here especially important to avoid races. |
| |
| Fixes: eea6653aae7b ("ARM: dts: Enable PMIC interrupts for exynos4412-odroid-common") |
| Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
| Link: https://lore.kernel.org/r/20201210212534.216197-6-krzk@kernel.org |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi |
| index 0d516529bf54..8735c5428677 100644 |
| --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi |
| +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi |
| @@ -265,7 +265,7 @@ |
| max77686: pmic@09 { |
| compatible = "maxim,max77686"; |
| interrupt-parent = <&gpx3>; |
| - interrupts = <2 IRQ_TYPE_NONE>; |
| + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&max77686_irq>; |
| reg = <0x09>; |
| -- |
| 2.30.2 |
| |
