| From 28144826725702dc94c6d1d9d4dee9d02003a5e0 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 10 Feb 2026 07:26:00 +0000 |
| Subject: drm/radeon: Add HAINAN clock adjustment |
| |
| From: decce6 <decce6@proton.me> |
| |
| [ Upstream commit 908d318f23d6b5d625bea093c5fc056238cdb7ff ] |
| |
| This patch limits the clock speeds of the AMD Radeon R5 M420 GPU from |
| 850/1000MHz (core/memory) to 800/950 MHz, making it work stably. This |
| patch is for radeon. |
| |
| Signed-off-by: decce6 <decce6@proton.me> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/radeon/si_dpm.c | 5 +++++ |
| 1 file changed, 5 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c |
| index fbf968e3f6d78..c688b4d914819 100644 |
| --- a/drivers/gpu/drm/radeon/si_dpm.c |
| +++ b/drivers/gpu/drm/radeon/si_dpm.c |
| @@ -2969,6 +2969,11 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, |
| max_sclk = 60000; |
| max_mclk = 80000; |
| } |
| + if ((rdev->pdev->device == 0x666f) && |
| + (rdev->pdev->revision == 0x00)) { |
| + max_sclk = 80000; |
| + max_mclk = 95000; |
| + } |
| } else if (rdev->family == CHIP_OLAND) { |
| if ((rdev->pdev->revision == 0xC7) || |
| (rdev->pdev->revision == 0x80) || |
| -- |
| 2.51.0 |
| |
