| From 02f037d641dc6672be5cfe7875a48ab99b95b154 Mon Sep 17 00:00:00 2001 |
| From: Toshi Kani <toshi.kani@hpe.com> |
| Date: Wed, 23 Mar 2016 15:41:57 -0600 |
| Subject: x86/mm/pat: Add support of non-default PAT MSR setting |
| |
| From: Toshi Kani <toshi.kani@hpe.com> |
| |
| commit 02f037d641dc6672be5cfe7875a48ab99b95b154 upstream. |
| |
| In preparation for fixing a regression caused by: |
| |
| 9cd25aac1f44 ("x86/mm/pat: Emulate PAT when it is disabled")' |
| |
| ... PAT needs to support a case that PAT MSR is initialized with a |
| non-default value. |
| |
| When pat_init() is called and PAT is disabled, it initializes the |
| PAT table with the BIOS default value. Xen, however, sets PAT MSR |
| with a non-default value to enable WC. This causes inconsistency |
| between the PAT table and PAT MSR when PAT is set to disable on Xen. |
| |
| Change pat_init() to handle the PAT disable cases properly. Add |
| init_cache_modes() to handle two cases when PAT is set to disable. |
| |
| 1. CPU supports PAT: Set PAT table to be consistent with PAT MSR. |
| 2. CPU does not support PAT: Set PAT table to be consistent with |
| PWT and PCD bits in a PTE. |
| |
| Note, __init_cache_modes(), renamed from pat_init_cache_modes(), |
| will be changed to a static function in a later patch. |
| |
| Signed-off-by: Toshi Kani <toshi.kani@hpe.com> |
| Reviewed-by: Thomas Gleixner <tglx@linutronix.de> |
| Cc: Andrew Morton <akpm@linux-foundation.org> |
| Cc: Andy Lutomirski <luto@amacapital.net> |
| Cc: Borislav Petkov <bp@alien8.de> |
| Cc: Borislav Petkov <bp@suse.de> |
| Cc: Brian Gerst <brgerst@gmail.com> |
| Cc: Denys Vlasenko <dvlasenk@redhat.com> |
| Cc: H. Peter Anvin <hpa@zytor.com> |
| Cc: Juergen Gross <jgross@suse.com> |
| Cc: Linus Torvalds <torvalds@linux-foundation.org> |
| Cc: Luis R. Rodriguez <mcgrof@suse.com> |
| Cc: Peter Zijlstra <peterz@infradead.org> |
| Cc: Toshi Kani <toshi.kani@hp.com> |
| Cc: elliott@hpe.com |
| Cc: konrad.wilk@oracle.com |
| Cc: paul.gortmaker@windriver.com |
| Cc: xen-devel@lists.xenproject.org |
| Link: http://lkml.kernel.org/r/1458769323-24491-2-git-send-email-toshi.kani@hpe.com |
| Signed-off-by: Ingo Molnar <mingo@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/x86/include/asm/pat.h | 2 - |
| arch/x86/mm/pat.c | 73 ++++++++++++++++++++++++++++++++------------- |
| arch/x86/xen/enlighten.c | 2 - |
| 3 files changed, 55 insertions(+), 22 deletions(-) |
| |
| --- a/arch/x86/include/asm/pat.h |
| +++ b/arch/x86/include/asm/pat.h |
| @@ -6,7 +6,7 @@ |
| |
| bool pat_enabled(void); |
| extern void pat_init(void); |
| -void pat_init_cache_modes(u64); |
| +void __init_cache_modes(u64); |
| |
| extern int reserve_memtype(u64 start, u64 end, |
| enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm); |
| --- a/arch/x86/mm/pat.c |
| +++ b/arch/x86/mm/pat.c |
| @@ -180,7 +180,7 @@ static enum page_cache_mode pat_get_cach |
| * configuration. |
| * Using lower indices is preferred, so we start with highest index. |
| */ |
| -void pat_init_cache_modes(u64 pat) |
| +void __init_cache_modes(u64 pat) |
| { |
| enum page_cache_mode cache; |
| char pat_msg[33]; |
| @@ -206,9 +206,6 @@ static void pat_bsp_init(u64 pat) |
| return; |
| } |
| |
| - if (!pat_enabled()) |
| - goto done; |
| - |
| rdmsrl(MSR_IA32_CR_PAT, tmp_pat); |
| if (!tmp_pat) { |
| pat_disable("PAT MSR is 0, disabled."); |
| @@ -217,15 +214,11 @@ static void pat_bsp_init(u64 pat) |
| |
| wrmsrl(MSR_IA32_CR_PAT, pat); |
| |
| -done: |
| - pat_init_cache_modes(pat); |
| + __init_cache_modes(pat); |
| } |
| |
| static void pat_ap_init(u64 pat) |
| { |
| - if (!pat_enabled()) |
| - return; |
| - |
| if (!cpu_has_pat) { |
| /* |
| * If this happens we are on a secondary CPU, but switched to |
| @@ -237,18 +230,32 @@ static void pat_ap_init(u64 pat) |
| wrmsrl(MSR_IA32_CR_PAT, pat); |
| } |
| |
| -void pat_init(void) |
| +static void init_cache_modes(void) |
| { |
| - u64 pat; |
| - struct cpuinfo_x86 *c = &boot_cpu_data; |
| + u64 pat = 0; |
| + static int init_cm_done; |
| |
| - if (!pat_enabled()) { |
| + if (init_cm_done) |
| + return; |
| + |
| + if (boot_cpu_has(X86_FEATURE_PAT)) { |
| + /* |
| + * CPU supports PAT. Set PAT table to be consistent with |
| + * PAT MSR. This case supports "nopat" boot option, and |
| + * virtual machine environments which support PAT without |
| + * MTRRs. In specific, Xen has unique setup to PAT MSR. |
| + * |
| + * If PAT MSR returns 0, it is considered invalid and emulates |
| + * as No PAT. |
| + */ |
| + rdmsrl(MSR_IA32_CR_PAT, pat); |
| + } |
| + |
| + if (!pat) { |
| /* |
| * No PAT. Emulate the PAT table that corresponds to the two |
| - * cache bits, PWT (Write Through) and PCD (Cache Disable). This |
| - * setup is the same as the BIOS default setup when the system |
| - * has PAT but the "nopat" boot option has been specified. This |
| - * emulated PAT table is used when MSR_IA32_CR_PAT returns 0. |
| + * cache bits, PWT (Write Through) and PCD (Cache Disable). |
| + * This setup is also the same as the BIOS default setup. |
| * |
| * PTE encoding: |
| * |
| @@ -265,10 +272,36 @@ void pat_init(void) |
| */ |
| pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) | |
| PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC); |
| + } |
| + |
| + __init_cache_modes(pat); |
| + |
| + init_cm_done = 1; |
| +} |
| + |
| +/** |
| + * pat_init - Initialize PAT MSR and PAT table |
| + * |
| + * This function initializes PAT MSR and PAT table with an OS-defined value |
| + * to enable additional cache attributes, WC and WT. |
| + * |
| + * This function must be called on all CPUs using the specific sequence of |
| + * operations defined in Intel SDM. mtrr_rendezvous_handler() provides this |
| + * procedure for PAT. |
| + */ |
| +void pat_init(void) |
| +{ |
| + u64 pat; |
| + struct cpuinfo_x86 *c = &boot_cpu_data; |
| + |
| + if (!pat_enabled()) { |
| + init_cache_modes(); |
| + return; |
| + } |
| |
| - } else if ((c->x86_vendor == X86_VENDOR_INTEL) && |
| - (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || |
| - ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) { |
| + if ((c->x86_vendor == X86_VENDOR_INTEL) && |
| + (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || |
| + ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) { |
| /* |
| * PAT support with the lower four entries. Intel Pentium 2, |
| * 3, M, and 4 are affected by PAT errata, which makes the |
| --- a/arch/x86/xen/enlighten.c |
| +++ b/arch/x86/xen/enlighten.c |
| @@ -1632,7 +1632,7 @@ asmlinkage __visible void __init xen_sta |
| * configuration. |
| */ |
| rdmsrl(MSR_IA32_CR_PAT, pat); |
| - pat_init_cache_modes(pat); |
| + __init_cache_modes(pat); |
| |
| /* keep using Xen gdt for now; no urgent need to change it */ |
| |