| From 675b09fa8d88392cbd9f6ae519e482a95c0d43d5 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 26 Jun 2020 10:06:02 +0200 |
| Subject: ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema |
| |
| From: Krzysztof Kozlowski <krzk@kernel.org> |
| |
| [ Upstream commit d7adfe5ffed9faa05f8926223086b101e14f700d ] |
| |
| Fix dtschema validator warnings like: |
| l2-cache@fffff000: $nodename:0: |
| 'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' |
| |
| Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC") |
| Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
| Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm/boot/dts/socfpga.dtsi | 2 +- |
| arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- |
| 2 files changed, 2 insertions(+), 2 deletions(-) |
| |
| diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi |
| index f0702d8063d9b..9a2db3df5edef 100644 |
| --- a/arch/arm/boot/dts/socfpga.dtsi |
| +++ b/arch/arm/boot/dts/socfpga.dtsi |
| @@ -676,7 +676,7 @@ ocram-ecc@ffd08144 { |
| }; |
| }; |
| |
| - L2: l2-cache@fffef000 { |
| + L2: cache-controller@fffef000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0xfffef000 0x1000>; |
| interrupts = <0 38 0x04>; |
| diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi |
| index f520cbff5e1c9..4d496479e1353 100644 |
| --- a/arch/arm/boot/dts/socfpga_arria10.dtsi |
| +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi |
| @@ -567,7 +567,7 @@ sdr: sdr@ffc25000 { |
| reg = <0xffcfb100 0x80>; |
| }; |
| |
| - L2: l2-cache@fffff000 { |
| + L2: cache-controller@fffff000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0xfffff000 0x1000>; |
| interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
| -- |
| 2.25.1 |
| |
