| From d723bc0f3167cc164ecbfb458e845c74d16b90ad Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 24 Mar 2021 18:23:52 -0700 |
| Subject: drm/msm: Fix a5xx/a6xx timestamps |
| |
| From: Rob Clark <robdclark@chromium.org> |
| |
| [ Upstream commit 9fbd3088351b92e8c2cef6e37a39decb12a8d5bb ] |
| |
| They were reading a counter that was configured to ALWAYS_COUNT (ie. |
| cycles that the GPU is doing something) rather than ALWAYS_ON. This |
| isn't the thing that userspace is looking for. |
| |
| Signed-off-by: Rob Clark <robdclark@chromium.org> |
| Acked-by: Jordan Crouse <jordan@cosmicpenguin.net> |
| Message-Id: <20210325012358.1759770-2-robdclark@gmail.com> |
| Signed-off-by: Rob Clark <robdclark@chromium.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- |
| drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- |
| 2 files changed, 4 insertions(+), 4 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c |
| index 5e11cdb207d8..0ca7e53db112 100644 |
| --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c |
| +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c |
| @@ -1240,8 +1240,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) |
| |
| static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) |
| { |
| - *value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO, |
| - REG_A5XX_RBBM_PERFCTR_CP_0_HI); |
| + *value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO, |
| + REG_A5XX_RBBM_ALWAYSON_COUNTER_HI); |
| |
| return 0; |
| } |
| diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c |
| index 83b50f6d6bb7..722c2fe3bfd5 100644 |
| --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c |
| +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c |
| @@ -1073,8 +1073,8 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) |
| /* Force the GPU power on so we can read this register */ |
| a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); |
| |
| - *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, |
| - REG_A6XX_RBBM_PERFCTR_CP_0_HI); |
| + *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, |
| + REG_A6XX_CP_ALWAYS_ON_COUNTER_HI); |
| |
| a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); |
| mutex_unlock(&perfcounter_oob); |
| -- |
| 2.30.2 |
| |
