| From 8f82eba8e70c517cd71545296b468ccdc4efb73f Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 23 Jan 2020 16:30:15 -0500 |
| Subject: drm/amd/display: Limit minimum DPPCLK to 100MHz. |
| |
| From: Yongqiang Sun <yongqiang.sun@amd.com> |
| |
| [ Upstream commit 6c81917a0485ee2a1be0dc23321ac10ecfd9578b ] |
| |
| [Why] |
| Underflow is observed when plug in a 4K@60 monitor with |
| 1366x768 eDP due to DPPCLK is too low. |
| |
| [How] |
| Limit minimum DPPCLK to 100MHz. |
| |
| Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> |
| Reviewed-by: Eric Yang <eric.yang2@amd.com> |
| Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 6 ++++++ |
| 1 file changed, 6 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |
| index dbf063856846e..5f683d118d2aa 100644 |
| --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |
| +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |
| @@ -149,6 +149,12 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, |
| rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); |
| } |
| |
| + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. |
| + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { |
| + if (new_clocks->dppclk_khz < 100000) |
| + new_clocks->dppclk_khz = 100000; |
| + } |
| + |
| if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { |
| if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) |
| dpp_clock_lowered = true; |
| -- |
| 2.20.1 |
| |
