| From 910721ab49e9b14335af4a349597b56ad78478a0 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 28 Jan 2020 10:31:19 -0800 |
| Subject: perf/x86/msr: Add Tremont support |
| |
| From: Kan Liang <kan.liang@linux.intel.com> |
| |
| [ Upstream commit 0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832 ] |
| |
| Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also |
| supported. |
| |
| Signed-off-by: Kan Liang <kan.liang@linux.intel.com> |
| Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> |
| Signed-off-by: Ingo Molnar <mingo@kernel.org> |
| Reviewed-by: Andi Kleen <ak@linux.intel.com> |
| Link: https://lkml.kernel.org/r/1580236279-35492-3-git-send-email-kan.liang@linux.intel.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/x86/events/msr.c | 3 ++- |
| 1 file changed, 2 insertions(+), 1 deletion(-) |
| |
| diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c |
| index 6f86650b3f77d..a949f6f55991d 100644 |
| --- a/arch/x86/events/msr.c |
| +++ b/arch/x86/events/msr.c |
| @@ -75,8 +75,9 @@ static bool test_intel(int idx, void *data) |
| |
| case INTEL_FAM6_ATOM_GOLDMONT: |
| case INTEL_FAM6_ATOM_GOLDMONT_D: |
| - |
| case INTEL_FAM6_ATOM_GOLDMONT_PLUS: |
| + case INTEL_FAM6_ATOM_TREMONT_D: |
| + case INTEL_FAM6_ATOM_TREMONT: |
| |
| case INTEL_FAM6_XEON_PHI_KNL: |
| case INTEL_FAM6_XEON_PHI_KNM: |
| -- |
| 2.20.1 |
| |
