| From 6a1ce99dc4bde564e4a072936f9d41f4a439140e Mon Sep 17 00:00:00 2001 |
| From: Anup Patel <anup.patel@wdc.com> |
| Date: Sun, 2 Feb 2020 16:32:02 +0530 |
| Subject: RISC-V: Don't enable all interrupts in trap_init() |
| |
| From: Anup Patel <anup.patel@wdc.com> |
| |
| commit 6a1ce99dc4bde564e4a072936f9d41f4a439140e upstream. |
| |
| Historically, we have been enabling all interrupts for each |
| HART in trap_init(). Ideally, we should only enable M-mode |
| interrupts for M-mode kernel and S-mode interrupts for S-mode |
| kernel in trap_init(). |
| |
| Currently, we get suprious S-mode interrupts on Kendryte K210 |
| board running M-mode NO-MMU kernel because we are enabling all |
| interrupts in trap_init(). To fix this, we only enable software |
| and external interrupt in trap_init(). In future, trap_init() |
| will only enable software interrupt and PLIC driver will enable |
| external interrupt using CPU notifiers. |
| |
| Fixes: a4c3733d32a7 ("riscv: abstract out CSR names for supervisor vs machine mode") |
| Signed-off-by: Anup Patel <anup.patel@wdc.com> |
| Reviewed-by: Atish Patra <atish.patra@wdc.com> |
| Tested-by: Palmer Dabbelt <palmerdabbelt@google.com> [QMEU virt machine with SMP] |
| [Palmer: Move the Fixes up to a newer commit] |
| Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> |
| Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/riscv/kernel/traps.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/arch/riscv/kernel/traps.c |
| +++ b/arch/riscv/kernel/traps.c |
| @@ -156,6 +156,6 @@ void __init trap_init(void) |
| csr_write(CSR_SCRATCH, 0); |
| /* Set the exception vector address */ |
| csr_write(CSR_TVEC, &handle_exception); |
| - /* Enable all interrupts */ |
| - csr_write(CSR_IE, -1); |
| + /* Enable interrupts */ |
| + csr_write(CSR_IE, IE_SIE | IE_EIE); |
| } |
