| From 8ccb4894e71a9ef2cf3cbf826ff8f5bb2e471322 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 26 Jul 2022 16:19:38 -0400 |
| Subject: drm/amd/display: Fix pixel clock programming |
| |
| From: Ilya Bakoulin <Ilya.Bakoulin@amd.com> |
| |
| [ Upstream commit 04fb918bf421b299feaee1006e82921d7d381f18 ] |
| |
| [Why] |
| Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned |
| between different HDMI lanes when using YCbCr420 10-bit pixel format. |
| |
| BIOS functions for transmitter/encoder control take pixel clock in kHz |
| increments, whereas the function for setting the pixel clock is in 100Hz |
| increments. Setting pixel clock to a value that is not on a kHz boundary |
| will cause the issue. |
| |
| [How] |
| Round pixel clock down to nearest kHz in 10/12-bpc cases. |
| |
| Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> |
| Acked-by: Brian Chang <Brian.Chang@amd.com> |
| Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> |
| Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 ++ |
| 1 file changed, 2 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c |
| index 845aa8a1027d8..c4040adb88b03 100644 |
| --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c |
| +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c |
| @@ -545,9 +545,11 @@ static void dce112_get_pix_clk_dividers_helper ( |
| switch (pix_clk_params->color_depth) { |
| case COLOR_DEPTH_101010: |
| actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; |
| + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; |
| break; |
| case COLOR_DEPTH_121212: |
| actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; |
| + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; |
| break; |
| case COLOR_DEPTH_161616: |
| actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; |
| -- |
| 2.35.1 |
| |
