| From 2251eb4c4bae05f88c175e217ca46a875e9e1d79 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 20 Oct 2022 11:46:51 -0400 |
| Subject: drm/amd/display: Enable timing sync on DCN32 |
| |
| From: Alvin Lee <Alvin.Lee2@amd.com> |
| |
| [ Upstream commit c3d3f35b725bf9c93bec6d3c056f6bb7cfd27403 ] |
| |
| Missed enabling timing sync on DCN32 because DCN32 has a different DML |
| param. |
| |
| Tested-by: Mark Broadworth <mark.broadworth@amd.com> |
| Reviewed-by: Martin Leung <Martin.Leung@amd.com> |
| Reviewed-by: Jun Lei <Jun.Lei@amd.com> |
| Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
| Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c |
| index d34e0f1314d9..bc4f48ea8d4c 100644 |
| --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c |
| +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c |
| @@ -1228,6 +1228,7 @@ int dcn20_populate_dml_pipes_from_context( |
| pipes[pipe_cnt].pipe.src.dcc = false; |
| pipes[pipe_cnt].pipe.src.dcc_rate = 1; |
| pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; |
| + pipes[pipe_cnt].pipe.dest.synchronize_timings = synchronized_vblank; |
| pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; |
| pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start |
| - timing->h_addressable |
| -- |
| 2.35.1 |
| |
