| From c530925f8e1e2f0429bd7a3d667e4ccabb9e6409 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Sat, 14 Dec 2024 16:17:01 +0800 |
| Subject: drm/rockchip: vop2: Fix the windows switch between different layers |
| |
| From: Andy Yan <andy.yan@rock-chips.com> |
| |
| [ Upstream commit 0ca953ac226eaffbe1a795f5e517095a8d494921 ] |
| |
| Every layer of vop2 should bind a window, and we also need to make |
| sure that this window is not used by other layer. |
| |
| 0x5 is a reserved layer sel value on rk3568, but it will select |
| Cluster3 on rk3588, configure unused layers to 0x5 will lead |
| alpha blending error on rk3588. |
| |
| When we bind a window from layerM to layerN, we move the old window |
| on layerN to layerM. |
| |
| Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") |
| Tested-by: Derek Foreman <derek.foreman@collabora.com> |
| Signed-off-by: Andy Yan <andy.yan@rock-chips.com> |
| Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
| Link: https://patchwork.freedesktop.org/patch/msgid/20241214081719.3330518-3-andyshrk@163.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 47 ++++++++++++++------ |
| 1 file changed, 34 insertions(+), 13 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c |
| index 1068f391b3e64..7619a0c42aada 100644 |
| --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c |
| +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c |
| @@ -1920,7 +1920,10 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) |
| struct drm_plane *plane; |
| u32 layer_sel = 0; |
| u32 port_sel; |
| - unsigned int nlayer, ofs; |
| + u8 layer_id; |
| + u8 old_layer_id; |
| + u8 layer_sel_id; |
| + unsigned int ofs; |
| u32 ovl_ctrl; |
| int i; |
| struct vop2_video_port *vp0 = &vop2->vps[0]; |
| @@ -1964,9 +1967,30 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) |
| for (i = 0; i < vp->id; i++) |
| ofs += vop2->vps[i].nlayers; |
| |
| - nlayer = 0; |
| drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { |
| struct vop2_win *win = to_vop2_win(plane); |
| + struct vop2_win *old_win; |
| + |
| + layer_id = (u8)(plane->state->normalized_zpos + ofs); |
| + |
| + /* |
| + * Find the layer this win bind in old state. |
| + */ |
| + for (old_layer_id = 0; old_layer_id < vop2->data->win_size; old_layer_id++) { |
| + layer_sel_id = (layer_sel >> (4 * old_layer_id)) & 0xf; |
| + if (layer_sel_id == win->data->layer_sel_id) |
| + break; |
| + } |
| + |
| + /* |
| + * Find the win bind to this layer in old state |
| + */ |
| + for (i = 0; i < vop2->data->win_size; i++) { |
| + old_win = &vop2->win[i]; |
| + layer_sel_id = (layer_sel >> (4 * layer_id)) & 0xf; |
| + if (layer_sel_id == old_win->data->layer_sel_id) |
| + break; |
| + } |
| |
| switch (win->data->phys_id) { |
| case ROCKCHIP_VOP2_CLUSTER0: |
| @@ -1995,17 +2019,14 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) |
| break; |
| } |
| |
| - layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, |
| - 0x7); |
| - layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, |
| - win->data->layer_sel_id); |
| - nlayer++; |
| - } |
| - |
| - /* configure unused layers to 0x5 (reserved) */ |
| - for (; nlayer < vp->nlayers; nlayer++) { |
| - layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7); |
| - layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); |
| + layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(layer_id, 0x7); |
| + layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(layer_id, win->data->layer_sel_id); |
| + /* |
| + * When we bind a window from layerM to layerN, we also need to move the old |
| + * window on layerN to layerM to avoid one window selected by two or more layers. |
| + */ |
| + layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, 0x7); |
| + layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, old_win->data->layer_sel_id); |
| } |
| |
| vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); |
| -- |
| 2.39.5 |
| |