| From stable+bounces-172669-greg=kroah.com@vger.kernel.org Sun Aug 24 02:31:19 2025 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Sat, 23 Aug 2025 20:31:08 -0400 |
| Subject: drm/amd/display: Don't overclock DCE 6 by 15% |
| To: stable@vger.kernel.org |
| Cc: "Timur Kristóf" <timur.kristof@gmail.com>, "Alex Deucher" <alexander.deucher@amd.com>, "Rodrigo Siqueira" <siqueira@igalia.com>, "Alex Hung" <alex.hung@amd.com>, "Sasha Levin" <sashal@kernel.org> |
| Message-ID: <20250824003109.2531974-1-sashal@kernel.org> |
| |
| From: Timur Kristóf <timur.kristof@gmail.com> |
| |
| [ Upstream commit cb7b7ae53b557d168b4af5cd8549f3eff920bfb5 ] |
| |
| The extra 15% clock was added as a workaround for a Polaris issue |
| which uses DCE 11, and should not have been used on DCE 6 which |
| is already hardcoded to the highest possible display clock. |
| Unfortunately, the extra 15% was mistakenly copied and kept |
| even on code paths which don't affect Polaris. |
| |
| This commit fixes that and also adds a check to make sure |
| not to exceed the maximum DCE 6 display clock. |
| |
| Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") |
| Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") |
| Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)") |
| Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> |
| Acked-by: Alex Deucher <alexander.deucher@amd.com> |
| Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> |
| Reviewed-by: Alex Hung <alex.hung@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| (cherry picked from commit 427980c1cbd22bb256b9385f5ce73c0937562408) |
| Cc: stable@vger.kernel.org |
| [ `MIN` => `min` ] |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 8 +++----- |
| 1 file changed, 3 insertions(+), 5 deletions(-) |
| |
| --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c |
| +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c |
| @@ -112,11 +112,9 @@ static void dce60_update_clocks(struct c |
| { |
| struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); |
| struct dm_pp_power_level_change_request level_change_req; |
| - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; |
| - |
| - /*TODO: W/A for dal3 linux, investigate why this works */ |
| - if (!clk_mgr_dce->dfs_bypass_active) |
| - patched_disp_clk = patched_disp_clk * 115 / 100; |
| + const int max_disp_clk = |
| + clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; |
| + int patched_disp_clk = min(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz); |
| |
| level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); |
| /* get max clock state from PPLIB */ |
