| From stable+bounces-172521-greg=kroah.com@vger.kernel.org Fri Aug 22 22:55:57 2025 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 22 Aug 2025 16:55:44 -0400 |
| Subject: PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining |
| To: stable@vger.kernel.org |
| Cc: Geraldo Nascimento <geraldogabriel@gmail.com>, Manivannan Sadhasivam <mani@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Robin Murphy <robin.murphy@arm.com>, Sasha Levin <sashal@kernel.org> |
| Message-ID: <20250822205544.1528134-2-sashal@kernel.org> |
| |
| From: Geraldo Nascimento <geraldogabriel@gmail.com> |
| |
| [ Upstream commit 114b06ee108cabc82b995fbac6672230a9776936 ] |
| |
| Rockchip controllers can support up to 5.0 GT/s link speed. But the driver |
| doesn't set the Target Link Speed currently. This may cause failure in |
| retraining the link to 5.0 GT/s if supported by the endpoint. So set the |
| Target Link Speed to 5.0 GT/s in the Link Control and Status Register 2. |
| |
| Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") |
| Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com> |
| [mani: fixed whitespace warning, commit message rewording, added fixes tag] |
| Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> |
| Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
| Tested-by: Robin Murphy <robin.murphy@arm.com> |
| Cc: stable@vger.kernel.org |
| Link: https://patch.msgid.link/0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1751322015.git.geraldogabriel@gmail.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ |
| 1 file changed, 4 insertions(+) |
| |
| --- a/drivers/pci/controller/pcie-rockchip-host.c |
| +++ b/drivers/pci/controller/pcie-rockchip-host.c |
| @@ -342,6 +342,10 @@ static int rockchip_pcie_host_init_port( |
| * Enable retrain for gen2. This should be configured only after |
| * gen1 finished. |
| */ |
| + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); |
| + status &= ~PCI_EXP_LNKCTL2_TLS; |
| + status |= PCI_EXP_LNKCTL2_TLS_5_0GT; |
| + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); |
| status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); |
| status |= PCI_EXP_LNKCTL_RL; |
| rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); |
