| From bf83b96f87ae2abb1e535306ea53608e8de5dfbb Mon Sep 17 00:00:00 2001 |
| From: Stephen Warren <swarren@nvidia.com> |
| Date: Thu, 3 Oct 2019 14:50:30 -0600 |
| Subject: clk: tegra: Mark fuse clock as critical |
| |
| From: Stephen Warren <swarren@nvidia.com> |
| |
| commit bf83b96f87ae2abb1e535306ea53608e8de5dfbb upstream. |
| |
| For a little over a year, U-Boot on Tegra124 has configured the flow |
| controller to perform automatic RAM re-repair on off->on power |
| transitions of the CPU rail[1]. This is mandatory for correct operation |
| of Tegra124. However, RAM re-repair relies on certain clocks, which the |
| kernel must enable and leave running. The fuse clock is one of those |
| clocks. Mark this clock as critical so that LP1 power mode (system |
| suspend) operates correctly. |
| |
| [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair |
| |
| Reported-by: Jonathan Hunter <jonathanh@nvidia.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Stephen Warren <swarren@nvidia.com> |
| Signed-off-by: Thierry Reding <treding@nvidia.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/clk/tegra/clk-tegra-periph.c | 6 +++++- |
| 1 file changed, 5 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/clk/tegra/clk-tegra-periph.c |
| +++ b/drivers/clk/tegra/clk-tegra-periph.c |
| @@ -799,7 +799,11 @@ static struct tegra_periph_init_data gat |
| GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), |
| GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), |
| GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), |
| - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), |
| + /* |
| + * Critical for RAM re-repair operation, which must occur on resume |
| + * from LP1 system suspend and as part of CCPLEX cluster switching. |
| + */ |
| + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL), |
| GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), |
| GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), |
| GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), |