| From 781a08d9740afa73357f1a60d45d7c93d7cca2dd Mon Sep 17 00:00:00 2001 |
| From: Tudor Ambarus <tudor.ambarus@microchip.com> |
| Date: Thu, 5 Dec 2019 09:54:01 +0000 |
| Subject: crypto: atmel-aes - Fix counter overflow in CTR mode |
| |
| From: Tudor Ambarus <tudor.ambarus@microchip.com> |
| |
| commit 781a08d9740afa73357f1a60d45d7c93d7cca2dd upstream. |
| |
| 32 bit counter is not supported by neither of our AES IPs, all implement |
| a 16 bit block counter. Drop the 32 bit block counter logic. |
| |
| Fixes: fcac83656a3e ("crypto: atmel-aes - fix the counter overflow in CTR mode") |
| Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> |
| Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/crypto/atmel-aes.c | 37 ++++++++++++------------------------- |
| 1 file changed, 12 insertions(+), 25 deletions(-) |
| |
| --- a/drivers/crypto/atmel-aes.c |
| +++ b/drivers/crypto/atmel-aes.c |
| @@ -91,7 +91,6 @@ |
| struct atmel_aes_caps { |
| bool has_dualbuff; |
| bool has_cfb64; |
| - bool has_ctr32; |
| bool has_gcm; |
| bool has_xts; |
| bool has_authenc; |
| @@ -1016,8 +1015,9 @@ static int atmel_aes_ctr_transfer(struct |
| struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); |
| struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); |
| struct scatterlist *src, *dst; |
| - u32 ctr, blocks; |
| size_t datalen; |
| + u32 ctr; |
| + u16 blocks, start, end; |
| bool use_dma, fragmented = false; |
| |
| /* Check for transfer completion. */ |
| @@ -1029,27 +1029,17 @@ static int atmel_aes_ctr_transfer(struct |
| datalen = req->nbytes - ctx->offset; |
| blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE); |
| ctr = be32_to_cpu(ctx->iv[3]); |
| - if (dd->caps.has_ctr32) { |
| - /* Check 32bit counter overflow. */ |
| - u32 start = ctr; |
| - u32 end = start + blocks - 1; |
| - |
| - if (end < start) { |
| - ctr |= 0xffffffff; |
| - datalen = AES_BLOCK_SIZE * -start; |
| - fragmented = true; |
| - } |
| - } else { |
| - /* Check 16bit counter overflow. */ |
| - u16 start = ctr & 0xffff; |
| - u16 end = start + (u16)blocks - 1; |
| - |
| - if (blocks >> 16 || end < start) { |
| - ctr |= 0xffff; |
| - datalen = AES_BLOCK_SIZE * (0x10000-start); |
| - fragmented = true; |
| - } |
| + |
| + /* Check 16bit counter overflow. */ |
| + start = ctr & 0xffff; |
| + end = start + blocks - 1; |
| + |
| + if (blocks >> 16 || end < start) { |
| + ctr |= 0xffff; |
| + datalen = AES_BLOCK_SIZE * (0x10000 - start); |
| + fragmented = true; |
| } |
| + |
| use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD); |
| |
| /* Jump to offset. */ |
| @@ -2553,7 +2543,6 @@ static void atmel_aes_get_cap(struct atm |
| { |
| dd->caps.has_dualbuff = 0; |
| dd->caps.has_cfb64 = 0; |
| - dd->caps.has_ctr32 = 0; |
| dd->caps.has_gcm = 0; |
| dd->caps.has_xts = 0; |
| dd->caps.has_authenc = 0; |
| @@ -2564,7 +2553,6 @@ static void atmel_aes_get_cap(struct atm |
| case 0x500: |
| dd->caps.has_dualbuff = 1; |
| dd->caps.has_cfb64 = 1; |
| - dd->caps.has_ctr32 = 1; |
| dd->caps.has_gcm = 1; |
| dd->caps.has_xts = 1; |
| dd->caps.has_authenc = 1; |
| @@ -2573,7 +2561,6 @@ static void atmel_aes_get_cap(struct atm |
| case 0x200: |
| dd->caps.has_dualbuff = 1; |
| dd->caps.has_cfb64 = 1; |
| - dd->caps.has_ctr32 = 1; |
| dd->caps.has_gcm = 1; |
| dd->caps.max_burst_size = 4; |
| break; |