| From 293fb05a2ce068b49bf594ea62f91dd4e16a5c74 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 3 Jul 2020 19:25:49 +0530 |
| Subject: Revert "i2c: cadence: Fix the hold bit setting" |
| |
| From: Raviteja Narayanam <raviteja.narayanam@xilinx.com> |
| |
| [ Upstream commit 0db9254d6b896b587759e2c844c277fb1a6da5b9 ] |
| |
| This reverts commit d358def706880defa4c9e87381c5bf086a97d5f9. |
| |
| There are two issues with "i2c: cadence: Fix the hold bit setting" commit. |
| |
| 1. In case of combined message request from user space, when the HOLD |
| bit is cleared in cdns_i2c_mrecv function, a STOP condition is sent |
| on the bus even before the last message is started. This is because when |
| the HOLD bit is cleared, the FIFOS are empty and there is no pending |
| transfer. The STOP condition should occur only after the last message |
| is completed. |
| |
| 2. The code added by the commit is redundant. Driver is handling the |
| setting/clearing of HOLD bit in right way before the commit. |
| |
| The setting of HOLD bit based on 'bus_hold_flag' is taken care in |
| cdns_i2c_master_xfer function even before cdns_i2c_msend/cdns_i2c_recv |
| functions. |
| |
| The clearing of HOLD bit is taken care at the end of cdns_i2c_msend and |
| cdns_i2c_recv functions based on bus_hold_flag and byte count. |
| Since clearing of HOLD bit is done after the slave address is written to |
| the register (writing to address register triggers the message transfer), |
| it is ensured that STOP condition occurs at the right time after |
| completion of the pending transfer (last message). |
| |
| Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> |
| Acked-by: Michal Simek <michal.simek@xilinx.com> |
| Signed-off-by: Wolfram Sang <wsa@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/i2c/busses/i2c-cadence.c | 9 ++------- |
| 1 file changed, 2 insertions(+), 7 deletions(-) |
| |
| diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c |
| index d917cefc5a19c..b136057182916 100644 |
| --- a/drivers/i2c/busses/i2c-cadence.c |
| +++ b/drivers/i2c/busses/i2c-cadence.c |
| @@ -382,10 +382,8 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) |
| * Check for the message size against FIFO depth and set the |
| * 'hold bus' bit if it is greater than FIFO depth. |
| */ |
| - if ((id->recv_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) |
| + if (id->recv_count > CDNS_I2C_FIFO_DEPTH) |
| ctrl_reg |= CDNS_I2C_CR_HOLD; |
| - else |
| - ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; |
| |
| cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); |
| |
| @@ -442,11 +440,8 @@ static void cdns_i2c_msend(struct cdns_i2c *id) |
| * Check for the message size against FIFO depth and set the |
| * 'hold bus' bit if it is greater than FIFO depth. |
| */ |
| - if ((id->send_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) |
| + if (id->send_count > CDNS_I2C_FIFO_DEPTH) |
| ctrl_reg |= CDNS_I2C_CR_HOLD; |
| - else |
| - ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; |
| - |
| cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); |
| |
| /* Clear the interrupts in interrupt status register. */ |
| -- |
| 2.25.1 |
| |