| From 4d163ad79b155c71bf30366dc38f8d2502f78844 Mon Sep 17 00:00:00 2001 |
| From: Michael Hennerich <michael.hennerich@analog.com> |
| Date: Thu, 14 Jan 2021 17:42:17 +0200 |
| Subject: spi: cadence: cache reference clock rate during probe |
| |
| From: Michael Hennerich <michael.hennerich@analog.com> |
| |
| commit 4d163ad79b155c71bf30366dc38f8d2502f78844 upstream. |
| |
| The issue is that using SPI from a callback under the CCF lock will |
| deadlock, since this code uses clk_get_rate(). |
| |
| Fixes: c474b38665463 ("spi: Add driver for Cadence SPI controller") |
| Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> |
| Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> |
| Link: https://lore.kernel.org/r/20210114154217.51996-1-alexandru.ardelean@analog.com |
| Signed-off-by: Mark Brown <broonie@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/spi/spi-cadence.c | 6 ++++-- |
| 1 file changed, 4 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/spi/spi-cadence.c |
| +++ b/drivers/spi/spi-cadence.c |
| @@ -119,6 +119,7 @@ struct cdns_spi { |
| void __iomem *regs; |
| struct clk *ref_clk; |
| struct clk *pclk; |
| + unsigned int clk_rate; |
| u32 speed_hz; |
| const u8 *txbuf; |
| u8 *rxbuf; |
| @@ -258,7 +259,7 @@ static void cdns_spi_config_clock_freq(s |
| u32 ctrl_reg, baud_rate_val; |
| unsigned long frequency; |
| |
| - frequency = clk_get_rate(xspi->ref_clk); |
| + frequency = xspi->clk_rate; |
| |
| ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
| |
| @@ -628,8 +629,9 @@ static int cdns_spi_probe(struct platfor |
| master->auto_runtime_pm = true; |
| master->mode_bits = SPI_CPOL | SPI_CPHA; |
| |
| + xspi->clk_rate = clk_get_rate(xspi->ref_clk); |
| /* Set to default valid value */ |
| - master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4; |
| + master->max_speed_hz = xspi->clk_rate / 4; |
| xspi->speed_hz = master->max_speed_hz; |
| |
| master->bits_per_word_mask = SPI_BPW_MASK(8); |