| From 27a82916acf70c267b56c6e06fc408dd1b960e97 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 13 Jun 2019 16:32:32 +0300 |
| Subject: dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" |
| |
| From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
| |
| [ Upstream commit c24a5c735f87d0549060de31367c095e8810b895 ] |
| |
| The commit |
| |
| 080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width") |
| |
| has been mistakenly submitted. The further investigations show that |
| the original code does better job since the memory side transfer size |
| has never been configured by DMA users. |
| |
| As per latest revision of documentation: "Channel minimum transfer size |
| (CHnMTSR)... For IOSF UART, maximum value that can be programmed is 64 and |
| minimum value that can be programmed is 1." |
| |
| This reverts commit 080edf75d337d35faa6fc3df99342b10d2848d16. |
| |
| Fixes: 080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width") |
| Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
| Signed-off-by: Vinod Koul <vkoul@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/dma/hsu/hsu.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c |
| index 29d04ca71d52e..15525a2b8ebd7 100644 |
| --- a/drivers/dma/hsu/hsu.c |
| +++ b/drivers/dma/hsu/hsu.c |
| @@ -64,10 +64,10 @@ static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc) |
| |
| if (hsuc->direction == DMA_MEM_TO_DEV) { |
| bsr = config->dst_maxburst; |
| - mtsr = config->src_addr_width; |
| + mtsr = config->dst_addr_width; |
| } else if (hsuc->direction == DMA_DEV_TO_MEM) { |
| bsr = config->src_maxburst; |
| - mtsr = config->dst_addr_width; |
| + mtsr = config->src_addr_width; |
| } |
| |
| hsu_chan_disable(hsuc); |
| -- |
| 2.20.1 |
| |
