| From d089f8f68f85118a3f559320707a6dd145dc98f8 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 1 May 2019 08:38:30 +0300 |
| Subject: IB/mlx5: Add missing XRC options to QP optional params mask |
| |
| From: Jack Morgenstein <jackm@dev.mellanox.co.il> |
| |
| [ Upstream commit 8f4426aa19fcdb9326ac44154a117b1a3a5ae126 ] |
| |
| The QP transition optional parameters for the various transition for XRC |
| QPs are identical to those for RC QPs. |
| |
| Many of the XRC QP transition optional parameter bits are missing from the |
| QP optional mask table. These omissions caused failures when doing XRC QP |
| state transitions. |
| |
| For example, when trying to change the response timer of an XRC receive QP |
| via the RTS2RTS transition, the new timer value was ignored because |
| MLX5_QP_OPTPAR_RNR_TIMEOUT bit was missing from the optional params mask |
| for XRC qps for the RTS2RTS transition. |
| |
| Fix this by adding the missing XRC optional parameters for all QP |
| transitions to the opt_mask table. |
| |
| Fixes: e126ba97dba9 ("mlx5: Add driver for Mellanox Connect-IB adapters") |
| Fixes: a4774e9095de ("IB/mlx5: Fix opt param mask according to firmware spec") |
| Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> |
| Signed-off-by: Leon Romanovsky <leonro@mellanox.com> |
| Signed-off-by: Jason Gunthorpe <jgg@mellanox.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/infiniband/hw/mlx5/qp.c | 21 +++++++++++++++++++++ |
| 1 file changed, 21 insertions(+) |
| |
| diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c |
| index a7bc89f5dae7e..4d906a7904818 100644 |
| --- a/drivers/infiniband/hw/mlx5/qp.c |
| +++ b/drivers/infiniband/hw/mlx5/qp.c |
| @@ -2324,6 +2324,11 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_Q |
| [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | |
| MLX5_QP_OPTPAR_Q_KEY | |
| MLX5_QP_OPTPAR_PRI_PORT, |
| + [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | |
| + MLX5_QP_OPTPAR_RAE | |
| + MLX5_QP_OPTPAR_RWE | |
| + MLX5_QP_OPTPAR_PKEY_INDEX | |
| + MLX5_QP_OPTPAR_PRI_PORT, |
| }, |
| [MLX5_QP_STATE_RTR] = { |
| [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | |
| @@ -2357,6 +2362,12 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_Q |
| MLX5_QP_OPTPAR_RWE | |
| MLX5_QP_OPTPAR_PM_STATE, |
| [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, |
| + [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | |
| + MLX5_QP_OPTPAR_RRE | |
| + MLX5_QP_OPTPAR_RAE | |
| + MLX5_QP_OPTPAR_RWE | |
| + MLX5_QP_OPTPAR_PM_STATE | |
| + MLX5_QP_OPTPAR_RNR_TIMEOUT, |
| }, |
| }, |
| [MLX5_QP_STATE_RTS] = { |
| @@ -2373,6 +2384,12 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_Q |
| [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | |
| MLX5_QP_OPTPAR_SRQN | |
| MLX5_QP_OPTPAR_CQN_RCV, |
| + [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | |
| + MLX5_QP_OPTPAR_RAE | |
| + MLX5_QP_OPTPAR_RWE | |
| + MLX5_QP_OPTPAR_RNR_TIMEOUT | |
| + MLX5_QP_OPTPAR_PM_STATE | |
| + MLX5_QP_OPTPAR_ALT_ADDR_PATH, |
| }, |
| }, |
| [MLX5_QP_STATE_SQER] = { |
| @@ -2384,6 +2401,10 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_Q |
| MLX5_QP_OPTPAR_RWE | |
| MLX5_QP_OPTPAR_RAE | |
| MLX5_QP_OPTPAR_RRE, |
| + [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | |
| + MLX5_QP_OPTPAR_RWE | |
| + MLX5_QP_OPTPAR_RAE | |
| + MLX5_QP_OPTPAR_RRE, |
| }, |
| }, |
| }; |
| -- |
| 2.20.1 |
| |
