| From 2a187d03352086e300daa2044051db00044cd171 Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= <mirq-linux@rere.qmqm.pl> |
| Date: Wed, 15 Jan 2020 10:54:35 +0100 |
| Subject: mmc: sdhci: fix minimum clock rate for v3 controller |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Michał Mirosław <mirq-linux@rere.qmqm.pl> |
| |
| commit 2a187d03352086e300daa2044051db00044cd171 upstream. |
| |
| For SDHCIv3+ with programmable clock mode, minimal clock frequency is |
| still base clock / max(divider). Minimal programmable clock frequency is |
| always greater than minimal divided clock frequency. Without this patch, |
| SDHCI uses out-of-spec initial frequency when multiplier is big enough: |
| |
| mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz |
| [for 480 MHz source clock divided by 1024] |
| |
| The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode. |
| |
| Fixes: c3ed3877625f ("mmc: sdhci: add support for programmable clock mode") |
| Cc: <stable@vger.kernel.org> # 4f6aa3264af4: mmc: tegra: Only advertise UHS modes if IO regulator is present |
| Cc: <stable@vger.kernel.org> |
| Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> |
| Acked-by: Adrian Hunter <adrian.hunter@intel.com> |
| Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl |
| Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/mmc/host/sdhci.c | 10 ++++++---- |
| 1 file changed, 6 insertions(+), 4 deletions(-) |
| |
| --- a/drivers/mmc/host/sdhci.c |
| +++ b/drivers/mmc/host/sdhci.c |
| @@ -3243,11 +3243,13 @@ int sdhci_setup_host(struct sdhci_host * |
| if (host->ops->get_min_clock) |
| mmc->f_min = host->ops->get_min_clock(host); |
| else if (host->version >= SDHCI_SPEC_300) { |
| - if (host->clk_mul) { |
| - mmc->f_min = (host->max_clk * host->clk_mul) / 1024; |
| + if (host->clk_mul) |
| max_clk = host->max_clk * host->clk_mul; |
| - } else |
| - mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; |
| + /* |
| + * Divided Clock Mode minimum clock rate is always less than |
| + * Programmable Clock Mode minimum clock rate. |
| + */ |
| + mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; |
| } else |
| mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
| |
