| From 3d18e33735a02b1a90aecf14410bf3edbfd4d3dc Mon Sep 17 00:00:00 2001 |
| From: Lyude <lyude@redhat.com> |
| Date: Thu, 11 May 2017 19:31:12 -0400 |
| Subject: drm/radeon: Unbreak HPD handling for r600+ |
| MIME-Version: 1.0 |
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| Content-Transfer-Encoding: 8bit |
| |
| From: Lyude <lyude@redhat.com> |
| |
| commit 3d18e33735a02b1a90aecf14410bf3edbfd4d3dc upstream. |
| |
| We end up reading the interrupt register for HPD5, and then writing it |
| to HPD6 which on systems without anything using HPD5 results in |
| permanently disabling hotplug on one of the display outputs after the |
| first time we acknowledge a hotplug interrupt from the GPU. |
| |
| This code is really bad. But for now, let's just fix this. I will |
| hopefully have a large patch series to refactor all of this soon. |
| |
| Reviewed-by: Christian König <christian.koenig@amd.com> |
| Signed-off-by: Lyude <lyude@redhat.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/radeon/cik.c | 4 ++-- |
| drivers/gpu/drm/radeon/evergreen.c | 4 ++-- |
| drivers/gpu/drm/radeon/r600.c | 2 +- |
| drivers/gpu/drm/radeon/si.c | 4 ++-- |
| 4 files changed, 7 insertions(+), 7 deletions(-) |
| |
| --- a/drivers/gpu/drm/radeon/cik.c |
| +++ b/drivers/gpu/drm/radeon/cik.c |
| @@ -7416,7 +7416,7 @@ static inline void cik_irq_ack(struct ra |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| - tmp = RREG32(DC_HPD5_INT_CONTROL); |
| + tmp = RREG32(DC_HPD6_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| @@ -7446,7 +7446,7 @@ static inline void cik_irq_ack(struct ra |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { |
| - tmp = RREG32(DC_HPD5_INT_CONTROL); |
| + tmp = RREG32(DC_HPD6_INT_CONTROL); |
| tmp |= DC_HPDx_RX_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| --- a/drivers/gpu/drm/radeon/evergreen.c |
| +++ b/drivers/gpu/drm/radeon/evergreen.c |
| @@ -4933,7 +4933,7 @@ static void evergreen_irq_ack(struct rad |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| - tmp = RREG32(DC_HPD5_INT_CONTROL); |
| + tmp = RREG32(DC_HPD6_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| @@ -4964,7 +4964,7 @@ static void evergreen_irq_ack(struct rad |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { |
| - tmp = RREG32(DC_HPD5_INT_CONTROL); |
| + tmp = RREG32(DC_HPD6_INT_CONTROL); |
| tmp |= DC_HPDx_RX_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| --- a/drivers/gpu/drm/radeon/r600.c |
| +++ b/drivers/gpu/drm/radeon/r600.c |
| @@ -3995,7 +3995,7 @@ static void r600_irq_ack(struct radeon_d |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
| - tmp = RREG32(DC_HPD5_INT_CONTROL); |
| + tmp = RREG32(DC_HPD6_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| --- a/drivers/gpu/drm/radeon/si.c |
| +++ b/drivers/gpu/drm/radeon/si.c |
| @@ -6330,7 +6330,7 @@ static inline void si_irq_ack(struct rad |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| - tmp = RREG32(DC_HPD5_INT_CONTROL); |
| + tmp = RREG32(DC_HPD6_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| @@ -6361,7 +6361,7 @@ static inline void si_irq_ack(struct rad |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { |
| - tmp = RREG32(DC_HPD5_INT_CONTROL); |
| + tmp = RREG32(DC_HPD6_INT_CONTROL); |
| tmp |= DC_HPDx_RX_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
