| From 41212e2fe72b26ded7ed78224d9eab720c2891e2 Mon Sep 17 00:00:00 2001 |
| From: Alex Deucher <alexander.deucher@amd.com> |
| Date: Mon, 2 Apr 2018 12:29:26 -0500 |
| Subject: drm/amdgpu: Fix PCIe lane width calculation |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Alex Deucher <alexander.deucher@amd.com> |
| |
| commit 41212e2fe72b26ded7ed78224d9eab720c2891e2 upstream. |
| |
| The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and |
| ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting |
| value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. |
| Port of the radeon fix to amdgpu. |
| |
| Acked-by: Christian Kรถnig <christian.koenig@amd.com> |
| Acked-by: Chunming Zhou <david1.zhou@amd.com> |
| Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553 |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/amd/amdgpu/si_dpm.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c |
| @@ -6449,9 +6449,9 @@ static void si_set_pcie_lane_width_in_sm |
| { |
| u32 lane_width; |
| u32 new_lane_width = |
| - (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; |
| + ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
| u32 current_lane_width = |
| - (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; |
| + ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
| |
| if (new_lane_width != current_lane_width) { |
| amdgpu_set_pcie_lanes(adev, new_lane_width); |
