| From d6827015e671cd17871c9b7a0fabe06c044f7470 Mon Sep 17 00:00:00 2001 |
| From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> |
| Date: Fri, 1 Feb 2019 13:02:27 +0530 |
| Subject: platform/x86: intel_pmc_core: Fix PCH IP name |
| |
| From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> |
| |
| commit d6827015e671cd17871c9b7a0fabe06c044f7470 upstream. |
| |
| For Cannonlake and Icelake, the IP name for Res_6 should be SPF i.e. |
| South Port F. No functional change is intended other than just renaming |
| the IP appropriately. |
| |
| Cc: "David E. Box" <david.e.box@intel.com> |
| Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> |
| Fixes: 291101f6a735 ("platform/x86: intel_pmc_core: Add CannonLake PCH support") |
| Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> |
| Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/platform/x86/intel_pmc_core.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/platform/x86/intel_pmc_core.c |
| +++ b/drivers/platform/x86/intel_pmc_core.c |
| @@ -205,7 +205,7 @@ static const struct pmc_bit_map cnp_pfea |
| {"CNVI", BIT(3)}, |
| {"UFS0", BIT(4)}, |
| {"EMMC", BIT(5)}, |
| - {"Res_6", BIT(6)}, |
| + {"SPF", BIT(6)}, |
| {"SBR6", BIT(7)}, |
| |
| {"SBR7", BIT(0)}, |
