| From 50643d491ef07c57634f90fd81710456201a4f73 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 15 Sep 2021 12:05:07 +0200 |
| Subject: drm/v3d: fix wait for TMU write combiner flush |
| |
| From: Iago Toral Quiroga <itoral@igalia.com> |
| |
| [ Upstream commit e4f868191138975f2fdf2f37c11318b47db4acc9 ] |
| |
| The hardware sets the TMUWCF bit back to 0 when the TMU write |
| combiner flush completes so we should be checking for that instead |
| of the L2TFLS bit. |
| |
| v2 (Melissa Wen): |
| - Add Signed-off-by and Fixes tags. |
| - Change the error message for the timeout to be more clear. |
| |
| Fixes spurious Vulkan CTS failures in: |
| dEQP-VK.binding_model.descriptorset_random.* |
| |
| Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader dispatch.") |
| Signed-off-by: Iago Toral Quiroga <itoral@igalia.com> |
| Reviewed-by: Melissa Wen <mwen@igalia.com> |
| Signed-off-by: Melissa Wen <melissa.srw@gmail.com> |
| Link: https://patchwork.freedesktop.org/patch/msgid/20210915100507.3945-1-itoral@igalia.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/v3d/v3d_gem.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c |
| index 19c092d75266b..1609a85429cef 100644 |
| --- a/drivers/gpu/drm/v3d/v3d_gem.c |
| +++ b/drivers/gpu/drm/v3d/v3d_gem.c |
| @@ -195,8 +195,8 @@ v3d_clean_caches(struct v3d_dev *v3d) |
| |
| V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); |
| if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & |
| - V3D_L2TCACTL_L2TFLS), 100)) { |
| - DRM_ERROR("Timeout waiting for L1T write combiner flush\n"); |
| + V3D_L2TCACTL_TMUWCF), 100)) { |
| + DRM_ERROR("Timeout waiting for TMU write combiner flush\n"); |
| } |
| |
| mutex_lock(&v3d->cache_clean_lock); |
| -- |
| 2.33.0 |
| |
