| From 862174ea613fe5a590d7880e535d44af417cfb15 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 10 Nov 2021 21:42:56 +0800 |
| Subject: net: hns3: allow configure ETS bandwidth of all TCs |
| |
| From: Guangbin Huang <huangguangbin2@huawei.com> |
| |
| [ Upstream commit 688db0c7a4a69ddc8b8143a1cac01eb20082a3aa ] |
| |
| Currently, driver only allow configuring ETS bandwidth of TCs according |
| to the max TC number queried from firmware. However, the hardware actually |
| supports 8 TCs and users may need to configure ETS bandwidth of all TCs, |
| so remove the restriction. |
| |
| Fixes: 330baff5423b ("net: hns3: add ETS TC weight setting in SSU module") |
| Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 2 +- |
| drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 9 +-------- |
| 2 files changed, 2 insertions(+), 9 deletions(-) |
| |
| diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c |
| index 9076605403a74..bb22d91f6e53e 100644 |
| --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c |
| +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c |
| @@ -124,7 +124,7 @@ static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets, |
| if (ret) |
| return ret; |
| |
| - for (i = 0; i < hdev->tc_max; i++) { |
| + for (i = 0; i < HNAE3_MAX_TC; i++) { |
| switch (ets->tc_tsa[i]) { |
| case IEEE_8021QAZ_TSA_STRICT: |
| if (hdev->tm_info.tc_info[i].tc_sch_mode != |
| diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c |
| index d98f0e2ec7aa3..8448607742a6b 100644 |
| --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c |
| +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c |
| @@ -974,7 +974,6 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev) |
| |
| static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev) |
| { |
| -#define DEFAULT_TC_WEIGHT 1 |
| #define DEFAULT_TC_OFFSET 14 |
| |
| struct hclge_ets_tc_weight_cmd *ets_weight; |
| @@ -987,13 +986,7 @@ static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev) |
| for (i = 0; i < HNAE3_MAX_TC; i++) { |
| struct hclge_pg_info *pg_info; |
| |
| - ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT; |
| - |
| - if (!(hdev->hw_tc_map & BIT(i))) |
| - continue; |
| - |
| - pg_info = |
| - &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; |
| + pg_info = &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; |
| ets_weight->tc_weight[i] = pg_info->tc_dwrr[i]; |
| } |
| |
| -- |
| 2.33.0 |
| |