| From bd8a6e31b87b39a03ab11820776363640440dbe0 Mon Sep 17 00:00:00 2001 |
| From: Vignesh Raghavendra <vigneshr@ti.com> |
| Date: Thu, 5 Dec 2019 12:29:33 +0530 |
| Subject: mtd: spi-nor: Split mt25qu512a (n25q512a) entry into two |
| |
| From: Vignesh Raghavendra <vigneshr@ti.com> |
| |
| commit bd8a6e31b87b39a03ab11820776363640440dbe0 upstream. |
| |
| mt25q family is different from n25q family of devices, even though manf |
| ID and device IDs are same. mt25q flash has bit 6 set in 5th byte of |
| READ ID response which can be used to distinguish it from n25q variant. |
| mt25q flashes support stateless 4 Byte addressing opcodes where as n25q |
| flashes don't. Therefore, have two separate entries for mt25qu512a and |
| n25q512a. |
| |
| Fixes: 9607af6f857f ("mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"") |
| Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> |
| Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/mtd/spi-nor/spi-nor.c | 9 +++++---- |
| 1 file changed, 5 insertions(+), 4 deletions(-) |
| |
| --- a/drivers/mtd/spi-nor/spi-nor.c |
| +++ b/drivers/mtd/spi-nor/spi-nor.c |
| @@ -2461,15 +2461,16 @@ static const struct flash_info spi_nor_i |
| { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, |
| { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
| + { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024, |
| + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | |
| + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
| + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | |
| + SPI_NOR_QUAD_READ) }, |
| { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, |
| { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, |
| { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096, |
| SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | |
| NO_CHIP_ERASE) }, |
| - { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024, |
| - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | |
| - SPI_NOR_QUAD_READ | |
| - SPI_NOR_4B_OPCODES) }, |
| { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, |
| |
| /* Micron */ |