| From 8e7a65aa70bcc1235a44e40ae0da5056525fe081 Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| Date: Wed, 7 Oct 2015 22:08:24 +0300 |
| Subject: drm/i915: Restore lost DPLL register write on gen2-4 |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| |
| commit 8e7a65aa70bcc1235a44e40ae0da5056525fe081 upstream. |
| |
| We accidentally lost the initial DPLL register write in |
| 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M |
| |
| The "three times for luck" hack probably saved us from a total |
| disaster. But anyway, bring the initial write back so that the |
| code actually makes some sense. |
| |
| Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca> |
| References: http://mid.gmane.org/CAN_QmVyMaArxYgEcVVsGvsMo7-6ohZr8HmF5VhkkL4i9KOmrhw@mail.gmail.com |
| Cc: Nick Bowler <nbowler@draconx.ca> |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/i915/intel_display.c | 2 ++ |
| 1 file changed, 2 insertions(+) |
| |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -1699,6 +1699,8 @@ static void i9xx_enable_pll(struct intel |
| I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); |
| } |
| |
| + I915_WRITE(reg, dpll); |
| + |
| /* Wait for the clocks to stabilize. */ |
| POSTING_READ(reg); |
| udelay(150); |
