| From 53f5285f11bd8480133eb623d34724900bc0aaed Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 25 May 2022 21:49:56 -0500 |
| Subject: pinctrl: sunxi: a83t: Fix NAND function name for some pins |
| |
| From: Samuel Holland <samuel@sholland.org> |
| |
| [ Upstream commit aaefa29270d9551b604165a08406543efa9d16f5 ] |
| |
| The other NAND pins on Port C use the "nand0" function name. |
| "nand0" also matches all of the other Allwinner SoCs. |
| |
| Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support") |
| Signed-off-by: Samuel Holland <samuel@sholland.org> |
| Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> |
| Link: https://lore.kernel.org/r/20220526024956.49500-1-samuel@sholland.org |
| Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++----- |
| 1 file changed, 5 insertions(+), 5 deletions(-) |
| |
| diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c |
| index 4ada80317a3b..b5c1a8f363f3 100644 |
| --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c |
| +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c |
| @@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = { |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| - SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ |
| + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| - SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ |
| + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| - SUNXI_FUNCTION(0x2, "nand"), /* DQS */ |
| + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ |
| SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| - SUNXI_FUNCTION(0x2, "nand")), /* CE2 */ |
| + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| SUNXI_FUNCTION(0x1, "gpio_out"), |
| - SUNXI_FUNCTION(0x2, "nand")), /* CE3 */ |
| + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ |
| /* Hole */ |
| SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), |
| SUNXI_FUNCTION(0x0, "gpio_in"), |
| -- |
| 2.35.1 |
| |
