| From foo@baz Mon Jul 23 08:34:58 CEST 2018 |
| From: Sanjeev Bansal <sanjeevb.bansal@broadcom.com> |
| Date: Mon, 16 Jul 2018 11:13:32 +0530 |
| Subject: tg3: Add higher cpu clock for 5762. |
| |
| From: Sanjeev Bansal <sanjeevb.bansal@broadcom.com> |
| |
| [ Upstream commit 3a498606bb04af603a46ebde8296040b2de350d1 ] |
| |
| This patch has fix for TX timeout while running bi-directional |
| traffic with 100 Mbps using 5762. |
| |
| Signed-off-by: Sanjeev Bansal <sanjeevb.bansal@broadcom.com> |
| Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com> |
| Reviewed-by: Michael Chan <michael.chan@broadcom.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/net/ethernet/broadcom/tg3.c | 9 +++++++++ |
| 1 file changed, 9 insertions(+) |
| |
| --- a/drivers/net/ethernet/broadcom/tg3.c |
| +++ b/drivers/net/ethernet/broadcom/tg3.c |
| @@ -9278,6 +9278,15 @@ static int tg3_chip_reset(struct tg3 *tp |
| |
| tg3_restore_clk(tp); |
| |
| + /* Increase the core clock speed to fix tx timeout issue for 5762 |
| + * with 100Mbps link speed. |
| + */ |
| + if (tg3_asic_rev(tp) == ASIC_REV_5762) { |
| + val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); |
| + tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val | |
| + TG3_CPMU_MAC_ORIDE_ENABLE); |
| + } |
| + |
| /* Reprobe ASF enable state. */ |
| tg3_flag_clear(tp, ENABLE_ASF); |
| tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | |
