| From f51b16c5efb39753dbb678c102ae390d9567927c Mon Sep 17 00:00:00 2001 |
| From: Thomas Gleixner <tglx@linutronix.de> |
| Date: Thu, 21 Feb 2019 12:36:50 +0100 |
| Subject: [PATCH 50/76] x86/msr-index: Cleanup bit defines |
| |
| commit d8eabc37310a92df40d07c5a8afc53cebf996716 upstream. |
| |
| Greg pointed out that speculation related bit defines are using (1 << N) |
| format instead of BIT(N). Aside of that (1 << N) is wrong as it should use |
| 1UL at least. |
| |
| Clean it up. |
| |
| [ Josh Poimboeuf: Fix tools build ] |
| |
| Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| Reviewed-by: Borislav Petkov <bp@suse.de> |
| Reviewed-by: Frederic Weisbecker <frederic@kernel.org> |
| Reviewed-by: Jon Masters <jcm@redhat.com> |
| Tested-by: Jon Masters <jcm@redhat.com> |
| [bwh: Backported to 4.9: Drop change to x86_energy_perf_policy, which doesn't |
| use msr-index.h here] |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/include/asm/msr-index.h | 34 ++++++++++++++++-------------- |
| tools/power/x86/turbostat/Makefile | 2 +- |
| 2 files changed, 19 insertions(+), 17 deletions(-) |
| |
| diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h |
| index d7813b118ac8..dc582c10586c 100644 |
| --- a/arch/x86/include/asm/msr-index.h |
| +++ b/arch/x86/include/asm/msr-index.h |
| @@ -1,6 +1,8 @@ |
| #ifndef _ASM_X86_MSR_INDEX_H |
| #define _ASM_X86_MSR_INDEX_H |
| |
| +#include <linux/bits.h> |
| + |
| /* |
| * CPU model specific register (MSR) numbers. |
| * |
| @@ -38,14 +40,14 @@ |
| |
| /* Intel MSRs. Some also available on other CPUs */ |
| #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ |
| -#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ |
| +#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ |
| #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ |
| -#define SPEC_CTRL_STIBP (1 << SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ |
| +#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ |
| #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ |
| -#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ |
| +#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ |
| |
| #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ |
| -#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ |
| +#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ |
| |
| #define MSR_IA32_PERFCTR0 0x000000c1 |
| #define MSR_IA32_PERFCTR1 0x000000c2 |
| @@ -62,20 +64,20 @@ |
| #define MSR_MTRRcap 0x000000fe |
| |
| #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a |
| -#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ |
| -#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ |
| -#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry */ |
| -#define ARCH_CAP_SSB_NO (1 << 4) /* |
| - * Not susceptible to Speculative Store Bypass |
| - * attack, so no Speculative Store Bypass |
| - * control required. |
| - */ |
| +#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ |
| +#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ |
| +#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ |
| +#define ARCH_CAP_SSB_NO BIT(4) /* |
| + * Not susceptible to Speculative Store Bypass |
| + * attack, so no Speculative Store Bypass |
| + * control required. |
| + */ |
| |
| #define MSR_IA32_FLUSH_CMD 0x0000010b |
| -#define L1D_FLUSH (1 << 0) /* |
| - * Writeback and invalidate the |
| - * L1 data cache. |
| - */ |
| +#define L1D_FLUSH BIT(0) /* |
| + * Writeback and invalidate the |
| + * L1 data cache. |
| + */ |
| |
| #define MSR_IA32_BBL_CR_CTL 0x00000119 |
| #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
| diff --git a/tools/power/x86/turbostat/Makefile b/tools/power/x86/turbostat/Makefile |
| index 8561e7ddca59..92be948c922d 100644 |
| --- a/tools/power/x86/turbostat/Makefile |
| +++ b/tools/power/x86/turbostat/Makefile |
| @@ -8,7 +8,7 @@ ifeq ("$(origin O)", "command line") |
| endif |
| |
| turbostat : turbostat.c |
| -CFLAGS += -Wall |
| +CFLAGS += -Wall -I../../../include |
| CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"' |
| |
| %: %.c |
| -- |
| 2.21.0 |
| |
